el00
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[SOLVED] what am I doing wrong in this VHDL code?
Hi,
I am a C programmer and I usually work with ucontrollers (I am not a student) and I am trying to learn VHDL.
I bought a nexys 2 board and I read some basics.
Now, I am trying to do this exercise (pag. 2):
**broken link removed**
however, I get the following error from the compiler:
(comes out from the line right after "with sel SELECT")
I think I am missing something from the course: in this case I have 2 components (see code below): what I want to do is to assign a specific subset of bits coming out from a port of counter to a port of leddec, selecting those bits according to signal sel (connected to mpx coming out from counter).
I know I am doing something wrong, but I cannot get the point.
Thank you for your help.
Now, this is my code:
module "hexcount.vhd":
module "leddec.vhd":
module "counter.vhd":
Hi,
I am a C programmer and I usually work with ucontrollers (I am not a student) and I am trying to learn VHDL.
I bought a nexys 2 board and I read some basics.
Now, I am trying to do this exercise (pag. 2):
**broken link removed**
however, I get the following error from the compiler:
Code:
"hexcount.vhd" Line 30. Type of Sout is incompatible with type of <=.I think I am missing something from the course: in this case I have 2 components (see code below): what I want to do is to assign a specific subset of bits coming out from a port of counter to a port of leddec, selecting those bits according to signal sel (connected to mpx coming out from counter).
I know I am doing something wrong, but I cannot get the point.
Thank you for your help.
Now, this is my code:
module "hexcount.vhd":
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hexcount is
Port ( clk_50MHz : in STD_LOGIC;
anode : out STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end hexcount;
architecture Behavioral of hexcount is
component counter is
Port ( clk : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (15 downto 0);
mpx: out STD_LOGIC_VECTOR (1 downto 0)); -- 2 bit to drive leds
end component;
component leddec is
Port ( dig : in STD_LOGIC_VECTOR (1 downto 0);
data : in STD_LOGIC_VECTOR (3 downto 0);
anode: out STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal Sin: STD_LOGIC_VECTOR (15 downto 0);
signal Sout: STD_LOGIC_VECTOR (3 downto 0);
signal sel: STD_LOGIC_VECTOR (1 downto 0);
begin
C1: counter port map (clk=>clk_50MHz, count=>Sin, mpx=>sel);
L1: leddec port map (dig=>sel, data=>Sout, anode=>anode, seg=>seg);
with sel SELECT
Sout <= Sin(3 downto 0) after 0 ns when "00",
Sout <= Sin(7 downto 4) after 0 ns when "01",
Sout <= Sin(11 downto 8) after 0 ns when "10",
Sout <= Sin(15 downto 12) after 0 ns when "11";
end Behavioral;module "leddec.vhd":
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity leddec is
Port ( dig : in STD_LOGIC_VECTOR (1 downto 0);
data : in STD_LOGIC_VECTOR (3 downto 0);
anode: out STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end leddec;
architecture Behavioral of leddec is
begin
-- Turn on segments corresponding to 4-bit data word
seg <= "0000001" when data="0000" else
--0
"1001111" when data="0001" else
"0010010" when data="0010" else
"0000110" when data="0011" else
"1001100" when data="0100" else
"0100100" when data="0101" else
"0100000" when data="0110" else
"0001111" when data="0111" else
"0000000" when data="1000" else
"0000100" when data="1001" else
"0001000" when data="1010" else
"1100000" when data="1011" else
"0110001" when data="1100" else
"1000010" when data="1101" else
"0110000" when data="1110" else
"0111000" when data="1111" else
"1111111";
-- Turn on anode of 7-segment display addressed by 2-bit digit selector dig
anode <= "1110" when dig="00" else --0
"1101" when dig="01" else
--1
"1011" when dig="10" else
--2
"0111" when dig="11" else
--3
"1111";
end Behavioral;
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (15 downto 0);
mpx: out STD_LOGIC_VECTOR (1 downto 0)); -- 2 bit to drive leds
end counter;
architecture Behavioral of counter is
signal cnt39: STD_LOGIC_VECTOR (38 downto 0); -- 39 bit counter
--signal cnt16: STD_LOGIC_VECTOR (15 downto 0); -- 39 bit counter
begin
process(clk)
begin
if clk'event and clk='1' then -- on rising edge of clock
cnt39 <= cnt39+1; -- increment counter
end if;
end process;
--cnt16 <= cnt38 (38 downto 23);
count <= cnt39 (38 downto 23);
mpx <= cnt39 (18 downto 17);
end Behavioral;
Last edited: