Wellbody layer in tsmc

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shanmei

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For tsmc180, the nmos transistor layout has a layer of wellbody. There is no information on this layer from its design rule. Is it just a dummy layer? Thanks.
 

Could mean the p-substrate of the wafer, or - more likely because of its name - the p-substrate (= p-body) of an isolated p-well in n-well.
 
shanmei said:
For tsmc180, the nmos transistor layout has a layer of wellbody. There is no information on this layer from its design rule. Is it just a dummy layer? Thanks.
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If it's not in the design rules I'd look again, try looking for the GDS number or contact the tsmc support./
 
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