Welcome to the Verilog HDL Group, Please Introduce Yourself....

[bigdogguru]

Welcome to the Verilog HDL Group,

I'm far from an expert in Verilog. After coding in VHDL for three years, I grew tired of the seemingly endless syntactical dribble required for the simplest tasks in VHDL. So I took a look at Verilog, I instantly fell in love with the simple, concise, C like syntax and now I'm hooked.

Over the past few months, I have read several books and come across several Verilog related site on the Internet. So I thought, why not share them!

But, I can't do this alone! So feel to post any information or links you feel is relevant.

Thanks to all members of Verilog HDL,
Big Dog

 

[Alexium]

Greetings!
I am a graduating student from Ukraine. I'm by no means expert neither in Verilog, nor in HDL design in general, but I'm interested in HDL design field and looking forward to extend my understanding and knowledge of the domain. Since I have found zero (I mean ZERO!!) job opportunities for FPGA designer in my country, I want to create my own projects in my spare time, in order to not loose the skill.
I was using VHDL for about 3 years for creating various simple educational and personal projects for FPGA. I felt VHDL is way too overloaded with meaningless grammatics, but up to the time of learning Verilog a year ago I became so familiar with VHDL that I just couldn't switch to Verilog. I only can understand and modify existing Verilog code, but I'm feeling uncomfortable writing from scratch. Obviously, I need to improve my Verilog skill.

Thanks for creating the group, Big Dog!
Best regards,
Alex