[SOLVED] Weird problem with unstable bandgap circuit

[Btrend]

Hi all,
I faced a weird problem about the bandgap circuit.
problem:
I had do many analysis (AC, Tran, DC) about the bandgap circuit, with different
conditions (SS,FF,TT, different temperature, different VCC) , all the simulation showed that the bandgap were stable. But the real chip was unstable. attached are my circuit, and the measurement.
In the photo of the measurement, Vin is yellow, Vip is blue and BG pink.
As u see, BG is oscillated at about 125kHz.
Why the Vbg is oscillated ?
any kind of idea are appreciated !

thanks

 

[aryajur]

Re: unstable bandgap

In the schematic, does PD, PDB represent Power Down, Power Down Bar? When I once did a Bandgap, I got oscillations in my Simulations. I found the cause to be the startup circuit and how it is connected to the opamp. I would sure like to see how you implement the opamp.

 

[Btrend]

Re: unstable bandgap

In the schematic, does PD, PDB represent Power Down, Power Down Bar? When I once did a Bandgap, I got oscillations in my Simulations. I found the cause to be the startup circuit and how it is connected to the opamp. I would sure like to see how you implement the opamp.

yes, PD =power down, PDB=power down bar,
the startup is only high for a while during the startup process (VCC ramp up),
sure, the attached is my opamp, which is simply a 2-stage implementation.

 

[aryajur]

Re: unstable bandgap

On the 1st look, I think this may be the problem, the miller compensation RC network, tha cap being made up of the MOS capacitor, if you interchange the position of the MOS cap with the resistor, it should stabilize. At least it did for my case. I had checked the startup transient at many temperatures. On some temperatures it became unstable if the capacitor was connected to the output node but, if it was the other way around then it was stable.

 

[BigBoss]

unstable bandgap

BG supplies could not provide high currents. If it's connected current consuming device especially to a switched system ( like on-off devices ) it will be "seems in oscillation" but it's not true.
If this is open circuit voltage, you have a problem with stability ( maybe opamp..)
Last words...

Don't trust too much to simulators, their accuracy are depending only on the accuracy of the models...

 

[Freakwency]

Re: unstable bandgap

On the 1st look, I think this may be the problem, the miller compensation RC network, tha cap being made up of the MOS capacitor, if you interchange the position of the MOS cap with the resistor, it should stabilize. At least it did for my case. I had checked the startup transient at many temperatures. On some temperatures it became unstable if the capacitor was connected to the output node but, if it was the other way around then it was stable.

Do the positions of the MOS-cap and the resistor really matters or is it just the problem of the simulaor?

 

[rambus_ddr]

Re: unstable bandgap

I also think that the mos cap maybe a problem. Because the mos capacitor is not constant, which changed according to the voltage between the output voltage and mos gate voltage. so when the voltage on the mos capacitor is zero,the capacitor is min, and the dominant pole became near to unity frequency,and cause to be unstable or oscillate.

 

[Btrend]

Re: unstable bandgap

BG supplies could not provide high currents. If it's connected current consuming device especially to a switched system ( like on-off devices ) it will be "seems in oscillation" but it's not true.
If this is open circuit voltage, you have a problem with stability ( maybe opamp..)
Last words...

Don't trust too much to simulators, their accuracy are depending only on the accuracy of the models...

the output BG see only a high impedance node (input of another buffer). so BG did not supply much current.
thanks

Added after 7 minutes:

I also think that the mos cap maybe a problem. Because the mos capacitor is not constant, which changed according to the voltage between the output voltage and mos gate voltage. so when the voltage on the mos capacitor is zero,the capacitor is min, and the dominant pole became near to unity frequency,and cause to be unstable or oscillate.

I had considered this issue too, so I ran a step response ( added a noise-like step voltage at the node ip, and node in), and the loop were still stable. if the compensation varied with output voltage of OPamp, then I should got some oscillation after the test of step input.

thanks

 

[ccw27]

Re: unstable bandgap

Hmm this is an intriguing problem. Try adding input offset voltage caused by mismatch from your input devices and ramp the supply voltage. If possible run monte carlo analysis. Sweep corners and temperature.

If the circuit still does not oscillate than it would be pretty scary!! Also you should double-check your layout. Maybe you made a subtle error in layout. You may also want to do a posim.

From my experience you should be able to find the root cause of the oscillation in simulation if your real chip oscillates. And often it takes time and the cause is some inconspicuous error.

Good luck and let us know !

 

[rajath]

Re: unstable bandgap

Did you try simulating with a ramped PD and PDB voltage? Do this along with the normal ramped vcc voltage. This may be one of the reasons for the oscillaltion .. just a guess

 

[Btrend]

Re: unstable bandgap

Hmm this is an intriguing problem. Try adding input offset voltage caused by mismatch from your input devices and ramp the supply voltage. If possible run monte carlo analysis. Sweep corners and temperature.

If the circuit still does not oscillate than it would be pretty scary!! Also you should double-check your layout. Maybe you made a subtle error in layout. You may also want to do a posim.

From my experience you should be able to find the root cause of the oscillation in simulation if your real chip oscillates. And often it takes time and the cause is some inconspicuous error.

Good luck and let us know !

1. I had added the offset in the opamp to simulate, and the loop war still stable with different combination of corner & temperature.
2. I had do postsim too, but it was still stable
thanks

Added after 5 minutes:

Did you try simulating with a ramped PD and PDB voltage? Do this along with the normal ramped vcc voltage. This may be one of the reasons for the oscillaltion .. just a guess

the PD & PDB can be forced to low and high though PD pad .
that is I can control PD & PDB from outside of chip, so it should not be a problem.
thanks too!

 

[bamboo]

unstable bandgap

Hi Btrend,
Can you explain how the op work in whole loop to make sure vip = vin ? And you can simulate the loop gain and phase margin in whole loop to see if it's really stable. Maybe it will be helpful for you.

 

[Btrend]

Re: unstable bandgap

hi all,
thanks for all ur help, I am really appreciated.
After checked the layout over and over, I found some suspect problem.
so I did FIB to these points.
Today, I found the BG is stable and it was the desired voltage 1.25V.
the bandgap was stable finally
But I still got question about this phenomenon.
FIB point: as shown in the attchment

I think the layout of the resistor were the cause of the problem !?
I used P+ diff resistor, and R2 and R3 are all in the same nWell,
I guess there exist some resistance or signal path between R2 & R3 ,
so as to ip and in.
But I just can't figure out what is the real reason.

maybe someone can give me a clue !
thanks

 

[Btrend]

Re: unstable bandgap

Hi Btrend,
Can you explain how the op work in whole loop to make sure vip = vin ? And you can simulate the loop gain and phase margin in whole loop to see if it's really stable. Maybe it will be helpful for you.

I used the file in attachment to simulate AC characteristics.
by doing this, I was sure that the loop was stable.

 

[rajath]

Re: unstable bandgap

Did you try to extract the layout and then run the simulation. if the extraction rule file
is comprehensive, then it shud add all the parasitic capacitance/resistance, giving more accurate results, and also an idea of what went wrong in the layout

btw, how did you manage to fabricate your chip in one day?

 

[Btrend]

Re: unstable bandgap

Did you try to extract the layout and then run the simulation. if the extraction rule file
is comprehensive, then it shud add all the parasitic capacitance/resistance, giving more accurate results, and also an idea of what went wrong in the layout

btw, how did you manage to fabricate your chip in one day?

1.I did run the postsim on both the parasitic cap/resistance, but the parasitic device such as pdio, ndio were not extract.
2. no, i did not fabricate my chip in one day, I did some circuit repair through FIB (Focused Ion Beam) process.