If you examine the internal signals of a post-route simulation, it is normal to see many glitches in the combinatorial logic, but the glitches should disappear before the next clock edge, so the flops operate cleanly.
- Do you see the malfunction in post-route simulation, or in hardware?
- If you change the clock frequency, does the malfunction change too?
- Have you fully constrained the timing, and does your timing analyzer tell you that all constraints are met?