[SOLVED] Weird inversion behavior

[keyboardcowboy]

Weird compliment problem

I have a 32 bit reg, and 64 bit reg. I have to take the 2's complement of the 32 bit reg and assign it to the 64 bit reg. Here is how I tried doing it

reg [63:0] a;
reg [31:0] b;

a <= (~b)+1

The complement went fine but when it gets assigned to "a" the, bits 63 to 32 of "a" are all set to 1 automatically even though I have assigned 0 to "a" before

To fix this issue I made another 32 bit reg "c", assigned the complement of "b" to "c", and then assigned " c" to "a" it worked this time, but I am a bit confused as to why in the case of direct assignment the upper bits of "a" are all set to 1

 

[Ashish Agrawal]

Re: Weird compliment problem

As per my understanding simulation tool tries to match the bit width of each variable of RHS with the LHS. So first reg b is converted to 64 bits by appending 32 0's at MSB after that inversion happens. That's why you see 1's at MSBs.

PS : If you do the same in VHDL, there you have to define reg b bit width as 64 otherwise you will get the compilation error. While Verilog is having flexibility to use variables of different bit width in the same expression but designer needs to be aware of the results.

 

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keyboardcowboy,

If you wan't to assign a 32-bit 2's complement value to a 64-bit value then sign extension is necessary, if you want to use the 64-bit value as a 2's complement value later. If you don't perform the sign extension the 64-bit value will be wrongly interpreted as a positive value.