[SOLVED] we have trouble with RS232 TX VHDL code

[Ivan-Holm]

We are trying to do some homework making a RS232 transmitter...
This is what we made so far and there is a lot of faults it it.. but we don't know what. We think its something with the way we written the states. Please rewrite it to some useful syntax

this is what we made so far

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity RS232_TX is
    Port ( 
    Baud_clk_Par_Ser_Conv : in  STD_LOGIC;                          -- Baud rate CLK
                      TX  : out STD_LOGIC_VECTOR ( 10 downto 0 );   -- TX
                      Data: in  STD_LOGIC_VECTOR ( 7 downto 0  )    -- Data stream
          );  
              
end RS232_TX;
 
 
architecture RS232 of RS232_TX is
 
 
shared variable T_1 : std_logic_vector (3 downto 0);
--BEGIN MAIN PROCESS
--RS232_TX : process (Baud_clk_Par_Ser_Conv)
 
begin
 
    -- BEGIN PROCESS Counter_1
 
    Counter_1 : process (Baud_clk_Par_Ser_Conv)
    variable  T : integer range 0 to 11;
 
    begin                                                                   
 
        if Baud_clk_Par_Ser_Conv' event and (Baud_clk_Par_Ser_Conv = '1') then
 
                T := T+1;
                if T >= 11 then T := 0;
                end if;
                     T_1 := CONV_STD_LOGIC_VECTOR(T, 4);
                
        end if;
 
    end process;                                                        
 
    -- END PROCESS  Counter_1
    
    -- BEGIN PROCESS RS232_TX
 
    RS232_TX : process  (Data, Baud_clk_Par_Ser_Conv)
    variable TX_1 : STD_LOGIC_VECTOR ( 9 downto 0  );
  variable rs232 : STD_LOGIC_VECTOR ( 9 downto 0  );  
    Begin
    
        if (Baud_clk_Par_Ser_Conv ='1') then                    -- Baud rate CLK
 
            Case T_1 is
 
                When "0000"  => TX_1 <= rs232(0)<= "0";                -- Startbit
                
                --Data Stream
                When "0001"  => TX_1 <= Data(0);                       -- Data Stream 1
                When "0010"  => TX_1 <= Data(1);                       -- Data Stream 2
                When "0011"  => TX_1 <= Data(2);                       -- Data Stream 3
                When "0100"  => TX_1 <= Data(3);                       -- Data Stream 4
                When "0101"  => TX_1 <= Data(4);                       -- Data Stream 5 
                When "0110"  => TX_1 <= Data(5);                       -- Data Stream 6
                When "0111"  => TX_1 <= Data(6);                       -- Data Stream 7
                When "1000"  => TX_1 <= Data(7);                       -- Data Stream 8
        
                When "1001" => TX_1 <=  rs232(9)<="1";                 -- Stopbit (in binary)
                
                when others => null;                                   -- default state
 
            end Case;
        end if;
 
    TX <= TX_1;
 
    end process;
 
    -- END PROCESS  RS232_TX
 
--end process;
 
-- END PROCESS  Main
 
end RS232;

---

 

[TrickyDicky]

There are no problems with the code - perhaps the problem is with your design. But the second process isnt triggering on a clock. You need "clk'event and clk = '1' ", not just clk = '1'.

 

[Ivan-Holm]

we have try to change whot we think that is wrong but it still make erros with the type ? how shot we do that?
the error list:
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 66. Type of TX_1 is incompatible with type of rs232.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 69. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 70. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 71. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 72. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 73. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 74. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 75. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 76. Type of TX_1 is incompatible with type of Data.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 78. Type of TX_1 is incompatible with type of <=.
ERROR:HDLParsers:800 - "D:/UCN 2011/Digital 2sem/fpga/teatTemadigi/digitestTema.vhd" Line 85. Type of TX is incompatible with type of TX_1.

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity digitestTema is
    Port ( Baud_clk_Par_Ser_Conv : in  STD_LOGIC;               -- Baud rate CLK
           --Reset : in  STD_LOGIC;
           --Enable : in  STD_LOGIC;
              --Par_Data : in STD_LOGIC_VECTOR ( 7 downto 0 );
           --Ser_data : out  STD_LOGIC;
              
              --------------
              TX  : out STD_LOGIC ;   -- TX
 
              Data: in  STD_LOGIC_VECTOR ( 7 downto 0  )        -- Data stream
              );  
              
end digitestTema;
--variable T_1 : std_logic_vector (3 downto 0);
 
architecture rs232out of digitestTema is
 
 
shared variable T_1 : std_logic_vector (3 downto 0);
--BEGIN MAIN PROCESS
--RS232_TX : process (Baud_clk_Par_Ser_Conv)
 
begin
 
    -- BEGIN PROCESS Counter_1
 
    Counter_1 : process (Baud_clk_Par_Ser_Conv)
    variable  T : integer range 0 to 11;
 
    begin                                                                   
 
        if Baud_clk_Par_Ser_Conv' event and (Baud_clk_Par_Ser_Conv = '1') then
 
                T := T+1;
                if T >= 11 then T := 0;
                end if;
                     T_1 := CONV_STD_LOGIC_VECTOR(T, 4);
                --T_1 <= T;
        end if;
 
    end process;                                                        
 
    -- END PROCESS  Counter_1
    
    -- BEGIN PROCESS RS232_TX
 
    RS232_TX : process  (Data, Baud_clk_Par_Ser_Conv)
    variable TX_1 : STD_LOGIC_VECTOR ( 9 downto 0  );
  variable rs232 : STD_LOGIC_VECTOR ( 1 downto 0  );-- start stop bit
  variable Data : std_Logic_vector (7 downto 0);
 -- Data <= "01011001"; -- indsæt data
    Begin
    Data := "01100100"; -- indsæt data
     rs232 := "01";
        if (Baud_clk_Par_Ser_Conv ='1') then  -- Baud rate CLK
 
            Case T_1 is
 
                When "0000"  => TX_1 := rs232(0);   -- Startbit
                
                --Data Stream
                When "0001"  => TX_1 := Data(0);                       -- Data Stream 1
                When "0010"  => TX_1 := Data(1);                       -- Data Stream 2
                When "0011"  => TX_1 := Data(2);                       -- Data Stream 3
                When "0100"  => TX_1 := Data(3);                       -- Data Stream 4
                When "0101"  => TX_1 := Data(4);                       -- Data Stream 5 
                When "0110"  => TX_1 := Data(5);                       -- Data Stream 6
                When "0111"  => TX_1 := Data(6);                       -- Data Stream 7
                When "1000"  => TX_1 := Data(7);                       -- Data Stream 8
        
                When "1001" => TX_1 :=  rs232(1)<= '1';-- Stopbit (in binary)
                
                when others => null;                                    -- default state
 
            end Case;
        end if;
 
    TX <= TX_1;
 
    end process;
 
    
 
end rs232out;

---

 

[Ivan-Holm]

we were not quite finished but with the help we got worked some of it thanks anyway