rakeshk.r
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I guess there are several ways to find the odd or even count values. I have mentioned 1 method in full vhdl code and other 2 methods as snippet. I would like to know other methods to determine these odd or even count values and they should also be synthesizable. Could some one help me on this. Thank you.
-- alternative methods
-- method2:
if ((-1)**i =-1) then -- note! this is not synthesizable
-- odd counter values
else
-- even counter values
end if;
-- method3:
if (i(0)='1') then -- assume here, 'i' is declared as , i : unsigned (7 downto 0);
-- odd counter values
else
-- even counter values
end if;
Code:
library ieee;
use std_logic_1164.all;
use ieee.numeric_std.all;
entity blk1
port( clk : IN std_logic;
rst : IN std_logic;
x : OUT integer );
end blk1;
architecture test of blk1 is
begin
p0: process (clk,rst)
variable i : integer; -- counter variable
begin
if (rst = '1' ) then
i := 0;
x <= 0;
elsif (rising_edge(clk)) then
-- method1:
i := i+1;
if (i mod 2 /= 0) then
x <= i ; -- odd counter values
else
x <= i ; -- even counter values
end if;
end if;
end process;
end architecture blk1;-- method2:
if ((-1)**i =-1) then -- note! this is not synthesizable
-- odd counter values
else
-- even counter values
end if;
-- method3:
if (i(0)='1') then -- assume here, 'i' is declared as , i : unsigned (7 downto 0);
-- odd counter values
else
-- even counter values
end if;