[SOLVED] Ways to configure Ethernet PHY registers over mdio+mdc interface

[dpaul]

Hello,

Background:
I have a multi TEMAC v9.0 design implemented on the AC701 using Viv2015.4
The Xilinx TEMACs have RGMII interfaces to communicate with the PHYs. The PHYs used are Marvell 88E1510. I am using an FMC interface add-on card called EthernetFMAC (it has 4 PHYs).
The design works properly at Gigabit mode, but not under 100Mbps and 10Mbps modes.

Problem: I think the PHYs are not getting configured properly. The probable reason for Gigabit mode operation is that the PHY registers take a setting after hardware reset that facilitate operation at Gigabit mode.

My approach:
1> I tried to use the *_axi_lite_sm state-machine but it gets stuck at an intermediate state. I have already created a thread in the Xilinx forums where this particular problem is elaborated.
http://forums.xilinx.com/t5/Network...-to-configure-88E1510-PHYs-of-the/td-p/710388
This SM however can configure the 88E1116R Marvell PHYs that are available as the AC701 on-board PHY. The TEMAC rgmii example design runs successfully on the AC701.

2> I have hooked up a uB along with an mdio engine that can R/W the Marvell 88E1510 PHY registers. There is also an UART module that can print the R/W values of the PHY registers. I have configured the Marvell 88E1510 PHY IEEE register bits as they should be, then set it for auto-negotiation but still my TEMAC and the PHY fail to communicate with a remote Ethernet card that has auto-negotiation enabled (communication also doesn't take place if I force the remote Ethernet card to operate at 100Mbps full-duplex mode).

In my opinion I am setting the register bits correctly and have triple checked them for 100Mbps full-duplex configuration. I don't understand where I am going wrong.

Any more ideas on PHY configuration would be of great help.

 

[slutarius]

Have you read out those registers which you have writen into the PHY ?
If not, how can you make sure they were correctly configured ?

 

[dpaul]

BY method <2>.
My uB ELF files takes care of what and when to R/W from the PHY regs. AN associated UART i/f prints out what I read/write. In this method I allow the Xilinx SM to take over the TEMAC configuration, ONLY after the PHY config has been finished.

 

[slutarius]

So I see nothing strange with the register setting. Probably, the order of register settings could be different between PHY devices.

 

[vGoodtimes]

out of curiosity, is auto-mdix enabled for 10/100 by default? 1000BASE-T has this feature, and PHY vendors have ported it back to 10/100 IIRC.

This is what makes it so you don't need crossover vs patch cables anymore. Is it possible that 10/100 works due to a cable issue that the example design can handle, but the user design can't?

you can also monitor the RGMII interface to see if clock rates change for both tx and rx clock, you can ensure the local EMAC also gets set up correctly. you may need to issue resets to both EMAC and PHY -- check the documentation to see when certain settings can take effect. IIRC, there are some that must be triggered by another register access or some other control input.

 

[dpaul]

out of curiosity, is auto-mdix enabled for 10/100 by default?

In Marvell PHY 88E1510 automatic crossover for all modes is enabled by default after h/w reset and I do not touch these bits later.

you can also monitor the RGMII interface to see if clock rates change for both tx and rx clock, you can ensure the local EMAC also gets set up correctly.

Are talking about simulation?
In simulation data exchg in RGMII mode for 3 speeds works perfectly.
I have modified and extended the Xilinx RGMII test-bench to suite my design. The limitation with the Xilinx TB is that the PHY negotiation is not modeled. It focuses on TEMAC operation.

The Xilinx TEMAC along with Marvell PHY 88E1510 communicates with the Ethernet i/f of my PC. The PC Eth is set to auto-nego. When I change the registers of the PHY to advertise 100Mbps full-duplex capability and then do a sw reset along with auto-nego enabled, then I can clearly see auto-nego taking place and after a few seconds, my PC Eth i/f software displays an auto-nego speed of 100Mbps. This means PHY to PHY link at 100Mbps is up and good.
But still there is no RGMII data transaction and I still have no reason to explain or debug this scenario.

- - - Updated - - -

From the above it is *most likely* that the PHY regs are getting correctly configured.

It seems that I now have to look at the RGMII signals at 10/100 speeds.

 

[vGoodtimes]

Are you sure the temac speed is set correctly as well?

 

[dpaul]

I am setting the speed exactly as done in the Xilinx RGMII eg_design.
Via the 2 GPIO DIP switches and the center GPIO push button sw to register the change in speed buttons.
Moreover I have brought out the two signals speedis10 and speedis100 (comes from the TEMAC config regs. deep within the core) as o/p ports and have connected them to two GPIO LEDs.

I will recheck tomorrow that the same speed settings are applied to the TEAMC and PHY.