[SOLVED] Waveform testbench Output Error

Status
Not open for further replies.
H

hby01

Newbie level 4
Joined
Feb 19, 2014
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
41
Hi. I'm working on this 32-bit kogge stone adder and I can't seem to get the wavform testbench right. The output signals are giving me H'UUUUUUUU and i cant seem to figure out the solution.
my testbench is as follows:
 
Last edited:

Since you didn't include the ksa.vhd file, I can only guess that you didn't connect the Sum output in that file, U means Unassigned/Unknown in simulation.

Regards
 

just sent you the ksa.vhd file. Hope you could check it and give me some feedback.
 

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

VHDL code:
 
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:12:20 03/31/2014 
-- Design Name: 
-- Module Name:    ksa - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
 
Last edited:

I tried adding G and P to process sensitivity list but nothing changed.
 

Why are you generating a clock? Cin is not a clock according to ksa.vhd
Why have you created an array of std_logic? why not use std_logic_vector? (you're going to make your life difficult)
As signals in the design only change when the input changes, you need to provide enough inputs to allow the output to ripple all the way through G and P.
 
Reactions: hby01

    H

    hby01

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…