Wave Impedance - ideal trace width TTL vs CMOS

[Jester]

I realize PCB dielectric comes into play, assume:
ground plane is 60 mils from signal for 2 layer board and 10 mils for 4 layer board

What are rule-of-thumb ideal trace widths for:

2 layer PCB 4 layer PCB
TTL
CMOS

Thank you

 

[marce]

Unless the tracks require a controlled impedance choose a width that fits with the component footprints, just keep them all the same.
If it does require controlled impedance you are going to have fun on 2 and 4 layer boards as generally the requirement for bog standard digital is 50R, so for a 2 layer board 2.5mm wide traces and for a 4 layer about 0.9mm traces.
But as said unless there is a requirement for controlled impedance don't bother...