Warnings using loop with signal

VHDL warnings using loop with signal

I have a problem with VHDL language about the use of loop instruction with signals. If I write the following code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_bit_1 is

port(a: in std_logic_vector(3 downto 0);
y: out std_logic_vector(2 downto 0));

end counter_bit_1;

architecture Behavioral of counter_bit_1 is
begin
process(a)
variable p: integer;
begin
p:=0;
for i in 3 downto 0 loop
if (a(i)='1') then p:=p+1;
end if;
end loop;
if p=0
then y<="000";
elsif p=1
then y<="001";
elsif p=2
then y<="010";
elsif p=3
then y<="011";
else y<="100";
end if;
end process;

end Behavioral;

It works perfectly and there aren't errors or warning.

While if I use the following code with a signal instead of a variable:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_bit_1 is

port(a: in std_logic_vector(3 downto 0);
y: out std_logic_vector(2 downto 0));

end counter_bit_1;

architecture Behavioral of counter_bit_1 is

signal p: std_logic_vector(2 downto 0);
begin
process(a)
begin
p<=(others=>'0');
for i in 3 downto 0 loop
if a(i)='1' then p<=p+"001";
end if;
end loop;
end process;

y<=p;

end Behavioral;

It doesn't work. The block should count the number of 1 bit in input. I get the following warnings:

WARNING:Xst:2170 - Unit counter_bit_1 : the following signal(s) form a combinatorial loop: Madd_p_share0000_lut<2>, p_share0000<2>.
WARNING:Xst:2170 - Unit counter_bit_1 : the following signal(s) form a combinatorial loop: p_share0000<1>, Madd_p_share0000_lut<1>.
WARNING:Xst:2170 - Unit counter_bit_1 : the following signal(s) form a combinatorial loop: Madd_p_share0000_cy<0>.

How can I implement the block using a signal?

It doesn't work. The block should count the number of 1 bit in input. I get the following warnings:

WARNING:Xst:2170 - Unit counter_bit_1 : the following signal(s) form a combinatorial loop: Madd_p_share0000_lut<2>, p_share0000<2>.
WARNING:Xst:2170 - Unit counter_bit_1 : the following signal(s) form a combinatorial loop: p_share0000<1>, Madd_p_share0000_lut<1>.
WARNING:Xst:2170 - Unit counter_bit_1 : the following signal(s) form a combinatorial loop: Madd_p_share0000_cy<0>.

How can I implement the block using a signal?

Click to expand...

Yes, it can't work. Why do you want do implement the construct with a signal?

The problem is that the LHS of a signal assignment is updated at the end of a delta cycle, after the end of the respective process. This means, that in an expression like
p<=p+"001",
the RHS signal is representing the result of the previous cycle. A signal can't be used to build a sum during an iteration loop. The LHS takes the values of the last assignment, all previous assignments within a delta cycle are ignored.

In a simulation, p would sum across simulation cycles. In synthesized hardware it can't achieve it for a combinational process.

Ok thanks, your explanation is very exhaustive. I can't use variables in VHDL because my theacer doesn't permit it. Anyway I could realize the following code using a signal:



library ieee;
use ieee.std_logic_1164.all;

entity one_counter is
port (a : in std_logic_vector (3 downto 0);
y : out std_logic_vector (2 downto 0)
);
end one_counter;

architecture beh of one_counter is

signal tmp : boolean;
begin
y(2) <= '1' when tmp else '0';

y(1 downto 0) <=
"00" when (a="0000") else
"11" when (a="0111") or (a="1011") or (a="1101") or
(a="1110") else
"01" when (a="0001") or (a="0010") or (a="0100") or
(a="1000") else "10";

tmp <= (a="1111");

end beh;


It works but in this case I only have an input with 4 bit, if for example I had an input with 12 bit this implementation wouldn't be possible so the only mode to resolve the problem is the use of a variable?

I don't get the purpose of the tmp boolean. You can also assign y(2) directly depending on an input value of "1111" or others.

Saying "don't use variables" without discussing an intended coding style systematically is pointless, and I don't want to take part in pointless discussions.

I think a suitable title for the second code in post#3 could be "how to make your life hard". It's a quite convincing argument why the iteration loop construct (which must use a variable) is the better behavioral code. Nevertheless there are other ways to implement a solution, and I presume the objective of "don't use variables" is to enforce thinking about it.

You can e.g. add the bit values explicitely
I'm also using the nasty STD_LOGIC_UNSIGNED library now, because it's given in your code example. In my opinion, it should be banned in VHDL teaching.

Re: VHDL warnings using loop with signal

Ok using the following code I removed the problem, now the code works without warnings.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_bit_1 is

port(a: in std_logic_vector(3 downto 0);
y: out std_logic_vector(2 downto 0));

end counter_bit_1;

architecture Behavioral of counter_bit_1 is
begin

y<="000"+a(0)+a(1)+a(2)+a(3);

end Behavioral;

Click to expand...

Anyway I am using the unsigned library, which library should I use?

std_logic_unsigned is non-standard VHDL. You should use the numeric_std library instead.
Std_logic_vector was never intended to be an integer - its just a collection of bits. The numeric_std library adds the types signed and unsigned for arithmatic.