Warnings in synthesis regarding the constraints file

Hi,

I have a problem regarding the constraints file.
DC compiler gives me warnings regarding these two lines in my constraint file:

set all_other_input_ports [remove_from_collection [all_inputs] [get_ports [list $all_clock_ports $obi_input_ports $irq_input_ports $early_input_ports]]]
set all_other_output_ports [remove_from_collection [all_outputs] [get_ports [list $all_clock_ports $obi_output_ports $sleep_output_ports $irq_output_ports]]]

The warnings:

Warning: Can't find ports matching 'instr_gnt_i instr_rvalid_i instr_rdata_i* data_gnt_i data_rvalid_i data_rdata_i*' in design 'cv32e40p_core'. (UID-95)
Warning: Can't find ports matching 'debug_req_i boot_addr_i* mtvec_addr_i* dm_halt_addr_i* hart_id_i* dm_exception_addr_i*' in design 'cv32e40p_core'. (UID-95)
Warning: Can't find ports matching 'instr_req_o instr_addr_o* data_req_o data_we_o data_be_o* data_addr_o* data_wdata_o*' in design 'cv32e40p_core'. (UID-95)
Warning: Can't find ports matching 'irq_ack_o irq_id_o*' in design 'cv32e40p_core'. (UID-95)

all these $strings are specific to your script, we have no way to tell you how to fix. nor can we tell what the original intent was. some sort of IO filtering? who knows

ThisIsNotSam said:

all these $strings are specific to your script, we have no way to tell you how to fix. nor can we tell what the original intent was. some sort of IO filtering? who knows

Click to expand...

I think i didn't explain my inquiry clearly, the ports that it is warning about already exist. So, I am asking if it is a syntax problem??

have you tried printing the lists one by one and seeing if it works? one of them must contain some port that doesn't exist. or some list is a string, not a list, so the * operand is not picking up what it should

Hi,

I'm also working on this cv32e40p core recently and having the exact same problem with you. Did you figure out how to solve this?

zorrolee777 said:

Hi,

I'm also working on this cv32e40p core recently and having the exact same problem with you. Did you figure out how to solve this?

Click to expand...

Hi,

I replaced these two lines with the following lines. It gives me no warning messages, but I am not sure if this is the best solution.

set f [all_inputs]
set a [get_ports $all_clock_ports]
set b [get_ports $obi_input_ports]
set c [get_ports $irq_input_ports]
set d [get_ports $early_input_ports]

set a_b [add_to_coll $a $b]
set abc [add_to_coll $a_b $c]
set abcd [add_to_coll $abc $d]

set all_other_input_ports [remove_from_coll $f $abcd]

set q [all_outputs]
set m [get_ports $all_clock_ports]
set n [get_ports $obi_output_ports]
set o [get_ports $sleep_output_ports]
set p [get_ports $irq_output_ports]

set m_n [add_to_coll $m $n]
set mno [add_to_coll $m_n $o]
set mnop [add_to_coll $mno $p]

set all_other_output_ports [remove_from_coll $q $mnop]

Mariammm said:

Hi,

I replaced these two lines with the following lines. It gives me no warning messages, but I am not sure if this is the best solution.

set f [all_inputs]
set a [get_ports $all_clock_ports]
set b [get_ports $obi_input_ports]
set c [get_ports $irq_input_ports]
set d [get_ports $early_input_ports]

set a_b [add_to_coll $a $b]
set abc [add_to_coll $a_b $c]
set abcd [add_to_coll $abc $d]

set all_other_input_ports [remove_from_coll $f $abcd]

set q [all_outputs]
set m [get_ports $all_clock_ports]
set n [get_ports $obi_output_ports]
set o [get_ports $sleep_output_ports]
set p [get_ports $irq_output_ports]

set m_n [add_to_coll $m $n]
set mno [add_to_coll $m_n $o]
set mnop [add_to_coll $mno $p]

set all_other_output_ports [remove_from_coll $q $mnop]

Click to expand...

Thanks! Also did you find any errors when doing the logic equivalence check?