[SOLVED] WARNING:Xst:1710 simple running light

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Hello,

i'm new to FPGA programming and now I've got a big problem. I already used the forum search but i couldn't find something useful
I'm using Verilog with the Spartan-3e board and Xilinx ISE Webpack 13.1. I tried to program a simple runnig light but there were several warnings so i reduced the code to a minimum but it still got those warnings:


I know that he sets my output to a constant value but i don't know why he does it. Here's my code:

Code: 
module my_wrapper(
         input In0,
         input In1,
         input CLK_50MHz,
	 input ROT_A,
	 input ROT_B,
	 input ROT_CENTER,
	 
    output [7:0] LED_ctrl
    );
	
	//----------------------------------------------------- DCM-Modul ------------------------------------------------
	wire CLK_DV;  // divided clock
	wire CLKIN_IBUFG;
	wire CLK0;  // unmodified 50 MHz DCM clock output
	
	my_dcm dcm_inst
	(
		.CLKIN_IN(CLK_50MHz), 
		.CLKDV_OUT(CLK_DV), 
		.CLKIN_IBUFG_OUT(CLKIN_IBUFG), 
		.CLK0_OUT(CLK0)
	);

	//------------------------------------------------ Timer --------------------------------------------------------
	
	wire timer_done;

	my_timer timer_inst (
          .clock(CLK_DV), 
          .reset(1'b1),
          .timer_start(1'b1),
          .timer_done(timer_done)
	);

       //----------------------------------------------------------------------------------------------------------------

	
	parameter init_state = 2'b00;
	parameter idle_state = 2'b01;
	parameter led_state = 2'b10;
	
	reg [1:0] state, state_next;
	
	reg [7:0] LEDs_next, LEDs;
	
	
	always @ (posedge CLK_DV) begin
		LEDs <= LEDs_next;
		state <= state_next;
	end
	
	always @ (state or timer_done or LEDs)  begin
		case(state)
			init_state:
			begin
				state_next = idle_state;
				LEDs_next = 8'b10101010; // new value
			end
			
			idle_state:
			begin
				state_next = idle_state;
				LEDs_next = LEDs; // keep old value
			end
		endcase
	end
	
	
	assign LED_ctrl[0] = LEDs[0];
	assign LED_ctrl[1] = LEDs[1];
	assign LED_ctrl[2] = LEDs[2];
	assign LED_ctrl[3] = LEDs[3];
	assign LED_ctrl[4] = LEDs[4];
	assign LED_ctrl[5] = LEDs[5];
	assign LED_ctrl[6] = LEDs[6];	
	assign LED_ctrl[7] = LEDs[7];
endmodule
The timer-modul works fine, i already tested it. I can't see the mistake in my code, im just trying to keep the value of LEDs in idle_state. Thanks

KR-500
 

Your assignment to LEDs is always same. I mean, you have never changed LEDs signal value..
So in optimization process, it directly connects to GND or VCC accordingly.
everytime be careful for the warnings. It's more important than errors.

For example, assign 01010101 to LEDs in another state, you don't get the warnings...
 
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    K

    KR-500

    Points: 2
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Hello,

thank you for your answer, but i still got a problem. The problem is that I want to keep the LEDs like they're by this line: "LEDs_next = LEDs;". You're right I've never changed the LED value, so i would expect them to be like this: 8'b10101010. But instead of this, they're all trimmed to GND like in the warning said. I coud understand it if they were trimmed to VCC and GND but they're only assigned to GND. So that's my main problem
In the meantime I assigned 8'b01010101 to the LEDs in the second state but it still got some errors:

So now the LEDs are trimmed to VCC and GND. It's kinda weird.
I hope you can help me, tahnks.

KR-500
 

if you look at your state machine, its always in "idle state". Is that Intended?

Look at your state machine code, there is a chance for latches as you have not completely used your states and more over timer done signal is not used.

re-check your code before you think of anything else.
 
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    K

    KR-500

    Points: 2
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Hi,

if you look at your state machine, its always in "idle state". Is that Intended?
Click to expand...

yes that was intended, i reduced the code to a minimum, because my first code didn't work. But here's the code i wrote first (just FSM):
Code: 
	parameter init_state = 2'b00;
	parameter idle_state = 2'b01;
	parameter led_state = 2'b10;
	
	reg [1:0] state, state_next;
	
	reg [7:0] LEDs_next;
	reg [7:0] LEDs;
	
	
	always @ (posedge CLK_DV) begin
		LEDs <= LEDs_next;
		state <= state_next;
	end
	
	always @ (state or timer_done or LEDs)  begin
		case(state)
			init_state:
			begin
				state_next = idle_state; // initial state
				LEDs_next = 8'b00000001; // initial value
			end
			
			idle_state:
			begin
				LEDs_next = LEDs; // keep LEDs
				if(timer_done == 1'b1)
					state_next = led_state; // if timer_done go to led_state
				else
					state_next = idle_state; // keep state
			end
			
			led_state:
			begin
				LEDs_next = LEDs << 1; // shift leds left
				state_next = idle_state; // go back to idle_state
			end
		endcase
	end
So what i intended was that when timer_done is high, he should got into "led_state" and shift LEDs left. Btw. it still has the same warnings that it will all be trimmed to GND, with this code. (My english isn't that good, i hope you can still understand me.) Thanks.

KR-500
 

I have modified the code, added reset and default value for state_next and LEDs_next to avoid latch inference.

Just add this piece of code in to your module, shouldnt get any warnings.

 
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    K

    KR-500

    Points: 2
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