Warning of files VHDL in FPGA design ( ..stx is missing ? )

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hannachifaten

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Hi every body ,
have you any idea what about this warning :
WARNINGrojectMgmt - File C:/....non_file/non_file.stx is missing
i can't synthesize my design even i have simulate this design before but when i come back to continue it has a lot of warning and erros , i don't do any thing


Any answer please
 

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