Warning in PEX Calibre Cadence Virtuoso

[soldier9810]

I am getting the following warnings in PEX for a layout of an inverter. Please help. There is no error in LVS and DRC.

WARNING: Contact layer ntap cannot appear as one of the connected layers on CONNECT statement. CONNECT statement ignored.
WARNING: Contact layer ptap cannot appear as one of the connected layers on CONNECT statement. CONNECT statement ignored.

 

[sidun.av]

1. Can you show us your CONNECT statements in Calibre? Most likely, the problem is in Connect by name statements.
2. Did you check ERC? You should provide correct power/ground nets there to get an adequate result.
3. Merging ptap and ntap with the device diffusion area is incorrect, because active devices will be affected. You should give it some spacing.

P.S. Usually, in IC layout we are considering gates to be in the same orientation across the chip and it is usually vertical. I think it would be useful to learn doing things in a common way since you are fresher. But you can use horizontal too, as long as you are consistent.

 

[soldier9810]

1. Can you show us your CONNECT statements in Calibre? Most likely, the problem is in Connect by name statements.
2. Did you check ERC? You should provide correct power/ground nets there to get an adequate result.
3. Merging ptap and ntap with the device diffusion area is incorrect, because active devices will be affected. You should give it some spacing.
View attachment 196879
P.S. Usually, in IC layout we are considering gates to be in the same orientation across the chip and it is usually vertical. I think it would be useful to learn doing things in a common way since you are fresher. But you can use horizontal too, as long as you are consistent.

I selected the body type for both the mosfets as integred. Should I have used deteached? Can you also please elaborate on your 1st point? I am very new to this software and IC Design itself. Where can I find CONNECT statements?

 

[sidun.av]

I selected the body type for both the mosfets as integred. Should I have used deteached? Can you also please elaborate on your 1st point? I am very new to this software and IC Design itself. Where can I find CONNECT statements?

If the body connection is done automatically (by selecting the option), that's probably okay for the particular circuit (CMOS inverter, not an analog circuit really). But it's better to select detached option for your own knowledge because in future you will be dealing with the arrays of multiple devices and having an integrated body for each of them is simply impractical. All these arrays are usually surrounded by a dedicated guard rings.

You can watch a tutorial on my channel:

CONNECT statements are used to connect nets in a layout without having a physical connection (Calibre shorts pins with nets namedin this statement). This option should be in LVS Options -> Connect (marked in red below).

For correct ERC results (highlights problems with the body connections) you should specify power/ground nets in LVS Options -> Supply (marked in green below).