Want verilog code for generating Trigger signal for 500ns

[AbinayaSivam]

Hi,

I am working with FPGA board. For my test, i am going to add the trigger logic in one side [One PC], and in other side the counter design will be added in XILIXN VIVADO and should start to give its counter after receiving the trigger signal.

For every trigger [500ns], the counter should start. To execute this task, i need the verilog code for Creating the Trigger Signal.

I am not very much familiar with Verilog code. So please can anyone the below code. If it is wrong, please update.

module counter(
    input clk,
    input reset,
    output [127:0] counter_out,                              // Output : 0 to 127 pins
    output trig
    );
    
    reg trig=0;
    reg [127:0] counter_out=0;
    reg [7:0] temp=0;
    
    always@(posedge clk)
    begin
    if(~reset)
        begin
        trig<=0;
        counter_out<=0;
        end
    else
        begin
        counter_out<=counter_out+1;
        temp<=temp+1;
        if(temp==25)
            begin
            temp<=0;
            trig<=~trig;
            end
        end
    end
endmodule

 

[dpaul]

So please can anyone the below code. If it is wrong, please update.

You can do it yourself by writing a test-bench for your code and verifying in simulation if it is behaving as expected.

Why are you using two counters? You can use the counter_out value for checking and the set the trigger accordingly.

btw - Antiquated Verilog syntax used!

 

[sreevenkjan]

Try writing a testbench and check what the counter does, as dpaul mentioned you do not need 2 counters. If you need the trigger at 500ns then I would suggest you to look at the counter value condition while setting the timescale in testbench.

 

[ads-ee]

    output [127:0] counter_out,                              // Output : 0 to 127 pins
    output trig
    );

What the heck are you trying to accomplish with this counter!?

A 128-bit counter could have started at the time of the big bang and been running at 500 MHz ever since and would have never rolled over.
That counter, using 500 MHz clock, would take approximately 21,580,000,000,000,000,000,000 years to rollover.

- - - Updated - - -

A 60-bit counter running at 500 MHz is potentially testable on hardware if you're willing to support the test for 73 years.

 

[niciki]

i am going to add the trigger logic in one side [One PC], and in other side the counter design will be added in XILIXN VIVADO and should start to give its counter after receiving the trigger signal.

For every trigger [500ns], the counter should start.

If I understand you correctly, you have a PC computer that generates trigger signal in 500 ns cycles to the FPGA board. You want to start a counter on every 'first trigger' and on every 'second trigger' you want that counter to be read and reset?

 

[ads-ee]

If I understand you correctly, you have a PC computer that generates trigger signal in 500 ns cycles to the FPGA board. You want to start a counter on every 'first trigger' and on every 'second trigger' you want that counter to be read and reset?

Not according to their code, which generates a trig signal output.

Unless the OP clarifies what they are attempting we can only guess their intent as they have a very confusing description of the problem and code that does not match the description