Mar 29, 2016 #1 S supriya123 Newbie level 3 Joined Mar 29, 2016 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 21 sir i want VHDL to VERILOG tool
Mar 29, 2016 #2 A amit.kumar11 Member level 5 Joined Jun 22, 2015 Messages 86 Helped 20 Reputation 40 Reaction score 19 Trophy points 8 Location Bangalore Activity points 471 Hi, Checkout these links: 1) http://www.syncad.com/verilog_vhdl_translator.htm 2)http://www.edautils.com/vhdl2verilog.html More you can search and get. Amit
Hi, Checkout these links: 1) http://www.syncad.com/verilog_vhdl_translator.htm 2)http://www.edautils.com/vhdl2verilog.html More you can search and get. Amit
Mar 29, 2016 #3 S supriya123 Newbie level 3 Joined Mar 29, 2016 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 21 what is the procedure to translate code using this tool. i could not option like translate
Mar 29, 2016 #4 A amit.kumar11 Member level 5 Joined Jun 22, 2015 Messages 86 Helped 20 Reputation 40 Reaction score 19 Trophy points 8 Location Bangalore Activity points 471 Hi, You wants to know how tool is translating or you want to use the tool? Amit
Mar 29, 2016 #5 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,833 Helped 317 Reputation 635 Reaction score 351 Trophy points 1,373 Location Germany Activity points 13,298 Sorry, in my dictionary there is no such phrase called 'spoon-feeding'! Amit Kumar has already done some work for you. Use google search and read carefully the search results is all I can suggest to you.
Sorry, in my dictionary there is no such phrase called 'spoon-feeding'! Amit Kumar has already done some work for you. Use google search and read carefully the search results is all I can suggest to you.
Mar 29, 2016 #6 S supriya123 Newbie level 3 Joined Mar 29, 2016 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 21 hii i want how tool is working(like language translation steps)
Mar 29, 2016 #7 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,823 Reputation 3,656 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,208 VHDL if =>tool translates=> Verilog if VHDL AND ==> Verilog & etc... these tools generally just perform some sort of lexical substitution and that is why they usually screw up to some extent. My preference hand convert or just leave it as is and run mixed mode simulations.
VHDL if =>tool translates=> Verilog if VHDL AND ==> Verilog & etc... these tools generally just perform some sort of lexical substitution and that is why they usually screw up to some extent. My preference hand convert or just leave it as is and run mixed mode simulations.
Mar 30, 2016 #8 dpaul Advanced Member level 5 Joined Jan 16, 2008 Messages 1,833 Helped 317 Reputation 635 Reaction score 351 Trophy points 1,373 Location Germany Activity points 13,298 supriya123 said: hii i want how tool is working(like language translation steps) Click to expand... Then perhaps find & read some IEEE/research-based papers (if they exist).
supriya123 said: hii i want how tool is working(like language translation steps) Click to expand... Then perhaps find & read some IEEE/research-based papers (if they exist).