want the equivalent verilog code for this

X : for i in 1 to 7 generate
process(clk,rst)
begin
if (rst = '0')then
d1(i) <= '1';
d2(i) <= '1';
d3(i) <= '1';
d4(i) <= '1';


elsif clk'event and clk = '1' then
d1(i) <= int_n(i);
d2(i) <= d1(i);
d3(i) <= d2(i);
d4(i) <= d3(i);
end if;
end process;


pend_set(i) <= d4(i) and (not d3(i)) and (not d2(i));


process(clk,rst)
begin
if (rst = '0')then
pend_n(i) <= '1';
elsif clk'event and clk= '1' then
if (pend_set(i) = '1') then
pend_n(i) <= '0';
elsif ((i = conv_integer(ack(2 downto 0))) and ack(3) = '0' and ack_n='1'
and ack_n_d3 ='0') then
pend_n(i) <= '1';
end if;
end if;
end process;
end generate X;


I am trying to convert this VHDL code to verilog.
I started with the generate statement then the problem is I can't write an always block inside a for loop in verilog.
Please suggest me how to write the above code in verilog correctly.

module try(input rst, clk, input [7:0] int_n);

reg [7:0] d1, d2, d3, d4, pend_n;
wire [7:0] pend_set;

always @(negedge rst or posedge clk)
begin
if (!rst)
begin
d1 <= 8'b11111111;
d2 <= 8'b11111111;
d3 <= 8'b11111111;
d4 <= 8'b11111111;
end
else
begin
d1 <= int_n;
d2 <= d1;
d3 <= d2;
d3 <= d3;
end
end


genvar i;
generate for (i=0; i<8; i=i+1)
begin: g_generate

assign pend_set = d4 & (~d3) & (~d2);

always @(negedge rst or posedge clk)
begin
if (!rst)
pend_n <= 1'b1;
else
begin
if (pend_set)
pend_n <= 1'b0;
end
end
end

endgenerate

endmodule

seem to compile with modelsim,
I did not complete wrotte your second process.

Try this code:

@rca its showing some errors in your code... however i thank u for giving an idea how to proceed

@vlsi_whiz What you pasted here is almost working. After a few corrections, I got no errors now. Thank you.