If this is a "waffle gate FET" then probably your extract rules
are too "ortho" and logically incapable of recognizing any but
basic "poly crosses active" gate areas and the S/D regions on
either side.
You may need to either improve the rules deck (add logic that
works) or mess with auxiliary views which the extractor can use
to "declare without understanding" that a certain layout is
such-and-such.
Now I don't think that a waffle FET brings much to the party, and
some of what it brings is not great (like, likely inferior hot-carrier
reliability and breakdown knee, from all the inside-corner D-G
field concentration). Used to see them on analog switches but
we did not find a great improvement in on resistance, a bit
inferior capacitance, and once we quit checking connectivity
with colored pencils it was just not worth supporting in the PDKs.