abu9022
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Vsim error 3807 types do not match between component and entity for port "ici"
Hi Friends
I have error while running the command "vsim -sdfmax /tb_msp/p0=verilog_iu_syn.sdf tb_msp"
ERROR
while I check the definition of error, it defined as " types of the port on the entity does not match the type of the port on the component which instantiates it"
proc.vhd(Instantiated file)
iu.vhd(original file)
Hi Friends
I have error while running the command "vsim -sdfmax /tb_msp/p0=verilog_iu_syn.sdf tb_msp"
ERROR
Code:
vsim -sdfmax /tb_msp/p0=verilog_iu_syn.sdf tb_msp
# vsim -sdfmax /tb_msp/p0=verilog_iu_syn.sdf tb_msp
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading work.target
# Loading ieee.std_logic_arith(body)
# Loading work.device
# Loading std.textio(body)
# Loading work.config
# Loading work.mmuconfig
# Loading work.sparcv8
# Loading work.iface
# Loading work.leonlib
# Loading work.tb_msp(behav)
# Loading work.tech_map
# Loading ieee.std_logic_unsigned(body)
# Loading work.debug(body)
# Loading work.leon(rtl)
# Loading work.amba
# Loading work.ambacomp
# Loading work.mcore(rtl)
# Loading work.rstgen(rtl)
# Loading work.ahbarb(rtl)
# Loading work.apbmst(rtl)
# Loading work.fpulib
# Loading work.proc(rtl)
# Loading work.iu(syn_verilog)
# ** Failure: (vsim-3807) Types do not match between component and entity for port "ici".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 9
# ** Failure: (vsim-3807) Types do not match between component and entity for port "ico".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 10
# ** Failure: (vsim-3807) Types do not match between component and entity for port "dci".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 11
# ** Failure: (vsim-3807) Types do not match between component and entity for port "dco".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 12
# ** Failure: (vsim-3807) Types do not match between component and entity for port "fpui".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 13
# ** Failure: (vsim-3807) Types do not match between component and entity for port "fpuo".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 14
# ** Failure: (vsim-3807) Types do not match between component and entity for port "iui".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 15
# ** Failure: (vsim-3807) Types do not match between component and entity for port "iuo".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 16
# ** Failure: (vsim-3807) Types do not match between component and entity for port "rfi".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 17
# ** Failure: (vsim-3807) Types do not match between component and entity for port "rfo".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 18
# ** Failure: (vsim-3807) Types do not match between component and entity for port "cpi".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 19
# ** Failure: (vsim-3807) Types do not match between component and entity for port "cpo".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 20
# ** Failure: (vsim-3807) Types do not match between component and entity for port "fpi".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 21
# ** Failure: (vsim-3807) Types do not match between component and entity for port "fpo".
# Time: 0 ps Iteration: 0 Instance: /tb_msp/p0/mcore0/proc0/iu0 File: /mnt/iscsi/Users/ee5113/zxv764/oldiu/leon2-1.0.30-xst/leon/iu.vhd Line: 22while I check the definition of error, it defined as " types of the port on the entity does not match the type of the port on the component which instantiates it"
proc.vhd(Instantiated file)
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.mmuconfig.all;
use work.iface.all;
use work.amba.all;
use work.fpulib.all;
use work.tech_map.all;
entity proc is
port (
rst : in std_logic;
clk : in clk_type; -- main clock
clkn : in clk_type; -- inverted main clock
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
iui : in iu_in_type;
iuo : out iu_out_type
);
end;
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.mmuconfig.all;
use work.iface.all;
use work.amba.all;
use work.fpulib.all;
use work.tech_map.all;
architecture rtl of proc is
component iu
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
ici : out icache_in_type; -- icache input
ico : in icache_out_type; -- icache output
dci : out dcache_in_type; -- dcache input
dco : in dcache_out_type; -- dcache output
fpui : out fpu_in_type; -- FPU input
fpuo : in fpu_out_type; -- FPU output
iui : in iu_in_type; -- system input
iuo : out iu_out_type; -- system output
rfi : out rf_in_type; -- register-file input
rfo : in rf_out_type; -- register-file output
cpi : out cp_in_type; -- CP input
cpo : in cp_out_type; -- CP output
fpi : out cp_in_type; -- FP input
fpo : in cp_out_type -- FP output
);
end component;
component cache
port (
rst : in std_logic;
clk : in clk_type;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
iuo : in iu_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_logic
);
end component;
component mmu_cache
port (
rst : in std_logic;
clk : in clk_type;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
iuo : in iu_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_logic
);
end component;
component cp
port (
rst : in std_logic; -- Reset
clk : in clk_type; -- main clock
iuclk : in clk_type; -- gated IU clock
holdn : in std_logic; -- pipeline hold
cpi : in cp_in_type;
cpo : out cp_out_type
);
end component;
component cachemem
port (
clk : in clk_type;
crami : in cram_in_type;
cramo : out cram_out_type
);
end component;
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal fpui : fpu_in_type;
signal fpuo : fpu_out_type;
signal cpi, fpi : cp_in_type;
signal cpo, fpo : cp_out_type;
signal holdn, pholdn, xholdn : std_logic;
signal iuol : iu_out_type;
signal rfi : rf_in_type; -- register-file input
signal rfo : rf_out_type; -- register-file output
signal crami : cram_in_type;
signal cramo : cram_out_type;
begin
holdn <= ico.hold and dco.hold and fpui.fpuholdn and cpo.holdn and fpo.holdn;
pholdn <= fpui.fpuholdn and cpo.holdn and fpo.holdn;
xholdn <= cpo.holdn and dco.hold and ico.hold;
iuo <= iuol;
-- integer unit and register file
[B][I] iu0 : iu port map (rst, clk, holdn, ici, ico, dci, dco, fpui, fpuo,
iui, iuol, rfi, rfo, cpi, cpo, fpi, fpo);[/I][/B] [B]Instantiated file[/B]
rf0 : regfile_iu generic map (RFIMPTYPE, RABITS, RDBITS, IREGNUM)
port map (rst, clk, clkn, rfi, rfo);
-- cache controller and memories
cx : if not M_EN generate
c0 : cache port map (rst, clk, ici, ico, dci, dco, iuol,
apbi, apbo, ahbi, ahbo, ahbsi, crami, cramo, pholdn);
end generate;
m0 : if M_EN generate
c0 : mmu_cache port map (rst, clk, ici, ico, dci, dco, iuol,
apbi, apbo, ahbi, ahbo, ahbsi, crami, cramo, pholdn);
end generate;
cmem0 : cachemem port map (clk, crami, cramo);
-- serial floating-point co-processor (optional)
fpsopt : if (FPIFTYPE = serial) generate
fpu0 : fpu_core port map (clk, fpui, fpuo); -- Meiko/LTH serial
end generate;
-- parallel floating-point co-processor (optional)
fppopt : if (FPIFTYPE = parallel) generate
fpc0 : if (FPCORE = grfpu) generate -- GR FPU/FPC
grfpc0 : grfpc port map (rst, clk, holdn, xholdn, fpi, fpo);
end generate;
fp1eu0 : if (FPCORE /= grfpu) generate -- Meiko/LTH parallel
fp0 : fp1eu port map (rst, clk, holdn, xholdn, fpi, fpo);
end generate;
end generate;
nofpc : if (FPIFTYPE /= parallel) generate
fpo.holdn <= '1';
fpo.ldlock <= '0';
fpo.ldlock <= '0';
fpo.ccv <= '1';
end generate;
-- co-processor (optional)
cpopt : if CPEN generate
cp0 : fp1eu port map (rst, clk, holdn, xholdn, cpi, cpo);
end generate;
nocp : if not CPEN generate
cpo.holdn <= '1';
cpo.ldlock <= '0';
end generate;
end ;iu.vhd(original file)
Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity iu is
port( rst, clk, holdn : in std_logic;
[I] ici : out std_logic_vector (94 downto 0);
ico : in std_logic_vector (68 downto 0);
dci : out std_logic_vector (116 downto 0);
dco : in std_logic_vector (127 downto 0);
fpui : out std_logic_vector (145 downto 0);
fpuo : in std_logic_vector (74 downto 0);
iui : in std_logic_vector (66 downto 0);
iuo : out std_logic_vector (517 downto 0);
rfi : out std_logic_vector (58 downto 0);
rfo : in std_logic_vector (63 downto 0);
cpi : out std_logic_vector (392 downto 0);
cpo : in std_logic_vector (172 downto 0);
fpi : out std_logic_vector (392 downto 0);
fpo : in std_logic_vector (172 downto 0)[/I] showing error here in italics
);
end iu;
architecture SYN_verilog of iu is
component INV_X4
port( A : in std_logic; ZN : out std_logic);
end component;
component AND4_X2
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;
component NAND4_X2
port( A1, A2, A3, A4 : in std_logic; ZN : out std_logic);
end component;