suquid29
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Hi
I was wondering what is the different, area wise, between >= and ==.
Lets say I want to start switch state in FSM (verilog, asic) with the condition cntr_t >= 4'h8.
(the counting is with a bit faster clock, so in the edge I'm checking it, it sometimes will be 8 and sometimes 9; there is sync).
Isn't it better to check only one bit with == ? (e.g cntr_t[3]==1'b1)
In general, how can I estimate area of different implementation of verilog code?
Is there some online tool?
I have synthesis tools, but its a big core ...
Thanks!
I was wondering what is the different, area wise, between >= and ==.
Lets say I want to start switch state in FSM (verilog, asic) with the condition cntr_t >= 4'h8.
(the counting is with a bit faster clock, so in the edge I'm checking it, it sometimes will be 8 and sometimes 9; there is sync).
Isn't it better to check only one bit with == ? (e.g cntr_t[3]==1'b1)
In general, how can I estimate area of different implementation of verilog code?
Is there some online tool?
I have synthesis tools, but its a big core ...
Thanks!