Here is a proof that it is NOT always faster.
Suppose the distributed resistance and the distributed capacitance are negligibly small, i.e., assume the wire to be driven is negligibly short. Then the waveform at the driver end of the wire is identical to the waveform at the receiver end of the wire. Negligible delay and negligible rise time degradation.
Since it is given that the wire is driven by a push pull CMOS inverter whose supplies are the digital voltage rails, the waveform at the driver end of the wire (== waveform at receiver too) is a full rail digital signal.
The current mode circuit puts that full rail digital signal through two subcircuits (M1-M4 is the first subcircuit, inverter is the second). The voltage mode circuit puts that full rail digital signal through only one subcircuit (inverter). Therefore voltage mode is faster because it has less delay in the receiver.
Thus we have exhibited a counterexample, in which current mode is slower than voltage mode. Thus "always faster" is false.