mogador
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Hi All,
Let's say that I have a FPGA and I configure one output with a drive strength of 8ma. At the other end of this signal there is another IC (very high input impedance) and I put parallel termination there: a 130 ohms resistor to 3v3 and a 82 ohms resistor to GND. I am trying to calculate the voltage at the output of the FPGA but it doesn't match with the voltage that I get with the simulator that I am using for signal integrity. Any help?
Another doubt that I have is what happens when the FPGA puts a '0' in this output. Then, the 8ma are imposed by the FPGA? Because I think that the FPGA only sets a path to ground. So what happens with the drive strength when the FPGA sets the output to '0'?
Many thanks!
Let's say that I have a FPGA and I configure one output with a drive strength of 8ma. At the other end of this signal there is another IC (very high input impedance) and I put parallel termination there: a 130 ohms resistor to 3v3 and a 82 ohms resistor to GND. I am trying to calculate the voltage at the output of the FPGA but it doesn't match with the voltage that I get with the simulator that I am using for signal integrity. Any help?
Another doubt that I have is what happens when the FPGA puts a '0' in this output. Then, the 8ma are imposed by the FPGA? Because I think that the FPGA only sets a path to ground. So what happens with the drive strength when the FPGA sets the output to '0'?
Many thanks!
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