Voltage comparator, using pre,post amplification and decision circuit with hysteresis

Hello,

I am trying to design a comparator. I have made the one in the images bellow.

However I have problems with making it work for difference voltages < 20mV. I would like a precision of at least 1 mV and delay of a couple of ns.
I want also small current, i'm using 50nA, for the biasing and 3.3V vdd.

From the image 3 there is clearly an offset. There are two examples; one with hysteresis and one without.

PMOS 30/2
output shift of decision circuit 10/10
both input diff 10/2
decision 10/2


Regards.

Indeed this image is too big for some screens... on bigger resolutions is fine. Sorry for this.




Here is my second attempt for the first image.
I replaced the normal current mirror with a wilson current mirror.

The "normal size" small schematic is impossible to see. It looks good only when I download it. The larger size schematic is as big as my neighbourhood and only one transistor can be seen at a time.
Thank you for making the Cadence image a positive instead of a negative.

Here is what your schematic looks like online:

The delay of comparator response depends to input signal slope and amplitude - we know this as "time walk". If You want to obtain 1mV precision, your input signal should have noise rms below 0.16mV. I don't know what is you final application but You need to consider this and also consider hysteresis size.

For fast response 50nA of brunch current and transistors working in weak inversion isn't a good idea, also for offset consideration.

Make two preamplifier stages, decision circuit as a 3rd stage which will be drive self-biased opamp followed by two or three inverters.
The preamplifiers could be a class AB stages. And believe electronic circuits with current working much better ;-)

Try to study following articles:
1. Super Class AB OTA:
**broken link removed**
**broken link removed**


2. Self biased opamp
https://ieeexplore.ieee.org/xpl/art...e=asc_p_Sequence&filter=AND(p_IS_Number:2417)