Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am trying to understand a circuit topology as shown in the figure.
Can anyone please help me understand what would be the voltage at the source of the PMOS (Mp) i.e at node A? I shown is a current source.
I am sorry can you please elaborate a little on this in terms of an expression. I am actually confused because of the presence of current source between Vdd and node A.
My basic aim is to find V1 which will be Va-Vgsp.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.