vlsi physical design:::

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Higher core utilization = higher routing density = routing will cause slower design = frequency will decrease.
 

Higher core utilization means that you have more cells in your design on the same area. Those cells require current, and you will have to connected them so you will have your routing resources decreased.
About higher current consumption - If you have power limitation, this might cause you to lower your frequency in order to reduce power.
About routing resources - In order to routing higher density design, your router will need to connect with detours which might cause critical path that will limit your frequency.
 

thank u very much for ur reply.....
how the utilization is directly proportional number of metal layers?

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sir what is the difference between high fanout network systhesis and clock tree synthesis?
 

More Metal layers means lesser area so the utilization is more.

Less metal layers means more are so the utilization is less.

Just assumption,Correct me if I am Wrong.
 

In my view
if utilization is increased the cell count ll increase,so the connectivity resources must increases so the metal layers are increased.
 

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