VLSI Frontend ASIC Modelling

Hi Folks,

I want to know that what is the importance of VLSI frontend modelling? We are developing the verilog hdl wrt functionality and timing . Then verifying them using functinal verification tool. Then doing the dft process (using tetramax,et tools) then generating the emulation (synthesizable) model. But the dft things we are doing pre synthesis netlist. So i want to know where we are standing?

It is helpfull if you guide......


Thanks
Priya

ASIC Front End Development:

• Specification Development
− Features definition, performance targets and algorithm development
− Technology and package selection for optimal costs and performance
− Die size estimate for target technology node
− Specification document development and review

• Micro-architecture Development
− Data-paths design, control design , and clock and power management
strategy
− Activity summary for power estimation and power budget evaluation
− Leverage of in house of IP and from third parties
− Micro-architecture documentation and review

• RTL Coding
− Design partitioning and coding and integration of silicon IP

• ASIC Implementation
− Pin out design, synthesis and power constraints development and
synthesis to target technology and library
− DFT design, test logic insertion & ATPG to achieve high test coverage

• Timing and Power Simulation
− Timing constraint development and timing and power simulation over
supply voltage and process corners based on estimated parasitics
− Review and release net list for back end ASIC implementation.