vlsi chip designing.....

Muthuraja.M · Aug 21, 2013

Hi ,

Is it possible to use clock gating in combinational circuits like full adder , multiplier etc..

Pls give me the design or verilog code?

chiranjeevinaidu · Aug 21, 2013

Hi,
clock gating used only between two sequential circuits or latches .
main concern of clock gating circuit to reduce the dynamic power

Thanks
chiranjeevi.pandamaneni

Muthuraja.M · Aug 22, 2013

Thanks...

How to design a buffer . Is buffer a latch or a inverter pairs ..

pls suggest me how to use buffer in modelsim ?

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