vlsi chip designing.....

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Same question is mine .

If anybody knows design a simple logic using power gating ?
 

You need some signals in your RTL to control the power switch of your voltage island.
After there is two ways to implement a voltage island:
1- with retention flop.
2- without retention flop, then you need some reset/reload sequence to restart as you want.
To see the impact on the simulation, you need to used UPF/CPF flow.

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1- retention flop must be provide by the std library.
2- usual std cell could be used, but extract logic is needed to have this properly "power-up" phase.

Also take care of the power switch design, power switch on/off sequence, function of the size of island.
 

RTL coding could be verilog, vhdl, don't care.
To impact the simulation it is better to used the UPF/CPF, because all supports is available.
You could create your own verilog feature but how do handle after that with the backend tool. It is possible but you need to take care to multiple stuffs that are already check via upf/cpf flow.
 

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