vlsi cell characterization

[utmseng]

I wish to use Hspice to find setup and hold time of my DFF.

I use the bisection method, as suggested by the manuals. For my positive edge clock, active high input and output DFF circuit, the simulation waveform shows that the data signal falls before the clock rising edge (seems to violating the hold time constraint). Why is it so?

Is it because my DFF is having negative hold time?

Can any one provide me with examples of hspice script to find the setup and hold time?

Thanks!

 

[wxy214]

cell characterization!

help!

how can I use hspice to calculate the setup time and hold time for DFF or Dlatch?

if I get delay information(tr tf tplh tphl Tsetup Thold) about digital standard cells, how can I add them to cell library, thus in cadence composer environment, I can run verilog_XL simulation!