VLSI: active and n+/p+

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yannik33

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Why differentiate VLSI-Systems between active and n+ resp. p+ ? If the p+ region is larger doesn't this increase the likelihood of an short circuit between drain and source (eg in the figure below there is a connection between drain and source side doesn't this lead to a short circuit?)?


(**broken link removed** ,p. 7)
 

Yes, I think you are right: MOSFETs shouldn't be in a highly doped region, they must be in lowly doped regions, as p-substrate for NMOS or n-well for PMOS.

This p. 7 of the DRM.pdf is surely erroneous. Of course a highly doped region for contact to GND respective VDD should be close to the MOSFET's source (or such a bulk contact ring around the transistor(s)), but never over the MOSFETs itselves.
 

Poly and Field Oxide (= !active) are both hard-masks for
P+ and N+.

Many flows allow butted N+/P+, there is no good reason to
enforce a global spacing rule (other than they never tried
it, to say that it's fine). There are good reasons to butt
body and source regions, like device compactness of
3T layouts.
 

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