(vlog-2110) & Verilog Modules Inqueries

Good Day Experts.

I'm a beginner in Verilog, and I'm simulating a 4-bit UP/DOWN counter, whose output is simultaneously compared -(via 4-bit comparator)- with input data_set (4 bits).

Actually, I've successfully simulated "4-bit UP/DOWN counter" using ModelSim. But for the "4-bit comparator".... I'm facing the following problems:


1. keep receiving: (vlog-2110) Illegal reference to net "data_set".
And when modified code as in below: Port mode is incompatible with declaration: counter (& data_set as well).

2. How can I modify code, to make comparator compares each instantaneous counter output with input data_set ?
Meaning: skip the comparator, and add if conditions inside counter module?
if yes: how can I define data_set & initialize it with some test value (say: 7 "0111") inside the counter module?

3. In general, if I need more modules to simulate.... please elaborate with some examples, how to connect/instantiate those modules:
(a) if they are written in the same verilog file ?
(b) if they are written in separate files (e.g.: counter module in "counter.v", comparator module in "comparator.v", D Flip Flop module in "D_FF.v", .... etc.) ?


My code -2110(in 1 same file)- is in below, with appreciation in advance.

AMM_77


############# CODE START #################

//##1. 4-bit UP/DOWN counter.

module four_bit_updown_counter(reset, enable, clock, counter);
input reset, enable, clock;
output [3:0] counter;
reg [3:0] counter;
reg [0:0] direction;

initial
direction = 1; // up count - initialization.

always @ (posedge reset)
begin
counter <= 0;
end

always @(posedge clock)
begin
if ((enable)&&(!reset))

if (direction == 1)
if (counter == 15)
begin
counter <= 14;
direction <= 0; // DOWN count.
end
else counter <= counter + 1;
else if (direction == 0)

if (counter == 0)
begin
counter <= 1;
direction = 1; // UP count.
end
else counter <= counter - 1;
end
endmodule

// output: counter



//##2. 4-bit comparator -- (comp#1)

module comparator_four_bit (a_lt_b_1, a_eq_b_1, counter,data_set);
// data_set = duty cycle

input counter, data_set;
output a_lt_b_1, a_eq_b_1;
reg [3:0] counter;
reg data_set;

initial
data_set = 4'b0111;

assign a_lt_b_1 = (counter < data_set);
assign a_eq_b_1 = (counter == data_set);

endmodule


// output: a_eq_b_1, a_lt_b_1

############# CODE START #################