Vivado synthesis fail. conditional expression could not be resolved to a constant.

Code Verilog - [expand]
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genvar i;
  generate
    for (i=0; i<M; i++) begin : VIRTUAL_CHANNELS
    // code here
    end
  endgenerate

Code Verilog - [expand]
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(parameter integer INPUT_QUEUE_DEPTH = 4,
  parameter integer N = 5,
  parameter integer M = 5)
 
    genvar i;
 
    generate
      for(i=0; i<N; i++) begin : GENERATE_VOQ
        LIB_VOQ #(.M(M), .DEPTH(INPUT_QUEUE_DEPTH))
          gen_LIB_VOQ (.clk,
                       .ce,
                       .reset_n,
                       .i_data(l_i_data[i]),         // Single input data from upstream router
                       .i_data_val(l_vc_req[i]),     // Valid from routecalc corresponds to required VC
                       .o_en(l_o_en[i]),
                       .o_data(l_data[i]),           // Single output data to switch
                       .o_data_val(l_output_req[i]), // Packed request word to SwitchControl
                       .i_en(l_en[i]));              // Packed grant word from SwitchControl
      end
    endgenerate

Code Verilog - [expand]
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for(i=0; i<N; i++) begin : GENERATE_VOQ

Code Verilog - [expand]
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//synthesizes
count_reg <= count_reg + 1;   // ads-ee: This is legal Verilog syntax
 
//fails
count_reg <= count_reg++;  // ads-ee: This isn't leagal Verilog or System Verilog syntax, so why are you giving a "C" sytnax example?
 
//for loop syntax
for(i=0; i<N; i=i+1) begin : GENERATE_VOQ   // ads-ee: this is leagal Verilog syntax
 
//for loop syntax
for(i=0; i<N; i++) begin : GENERATE_VOQ   // ads-ee: this is leagal System Verilog syntax, which Vivado does support for synthesis,
                                          // but according to the OP the parser has a problem with "for(" (no space) and doesn't with "for (" (with space).