[SOLVED] Vivado optimising logic and ILA issues

[sreevenkjan]

the clk is connected to the output of the FCLK_CLK0 from the processing system with a freq of 100MHz.rstn is a active low reset. rstn is '0' value.

 

[TrickyDicky]

have you connected rstn to '0' permenantly?

 

[sreevenkjan]

I have connected the clk to processing system clk and rstn is assigned '0'.

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in signal declarations it is connected to '0'...yes..

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yes i have connected the clk of the processing system to output of clk and then no i have not assigned rstn to '0'....it is in U state

 

[TrickyDicky]

rstn needs to be connected to somehitng - its the reset. Holidng it at 0 will hold the system in reset and if you compile it like this, anything that has a reset input will be removed, which will probably remove other parts of the design!

 

[sreevenkjan]

rstn needs to be connected to somehitng - its the reset. Holidng it at 0 will hold the system in reset and if you compile it like this, anything that has a reset input will be removed, which will probably remove other parts of the design!

rstn is not connected to '0'. if rstn = '0' then it resets.i am using the rst port of bram so therefore it is not tied to 0.

 

[sreevenkjan]

i tried removing the reset option and still I am unable to solve the problem.my bram contents are overwritten 4 times.can this be a problem??

 

[TrickyDicky]

If logic is being removed, it will be because:

1. A clock is stuck at '0' or '1'
2. A reset is stuck enabled
3. Muxes have a fixed selection.
4. Logic has no effect on an output pin (a pin on the FPGA, not an output from your logic).

You need to work out which one of these is happening in your project. Follow the warnings generated to trace the problem back.

 

[sreevenkjan]

hi,

the problem is solved...the warnings which said logic was being removed or being optimised was irrelevant or not important...the problem was with the ila IP from the xilinx coregen...the probes were needed to be added on the waveforms to see the output.