[virtuoso] problems with simulation using extracted layout

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Dr. von Rosenstein

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hi,

first: sorry for my bad english!

i want to simulate my circuit using the extracted view of the layout. at the "environment options" i added "analog_extracted" in the "Switch View List" as the first entry. then i created a new netlist (Simulation->Netlist->Create).
if i use ADE L, the simulation runs without errors. but if i use ADE XL i receive this message:

ADEXL-1 610: New variables were found for the following tests:
impedanz:RFDC_dio_T:1 {extraction, in, not, used)
Assign values to these variables before running simulations.


what do i wrong?

thanks for all help!
 

Perhaps you forgot to # uncomment your comment in the control file?
 

i don't understand what you mean. which control file?

this error occcurs only if i use ADE XL. if i use ADE L i did not receive this message. i think this message would occur also in ADE L if i have realy forgot to uncomment something.

can anyone help me please? than you!
 

Hello Herr Dr.

Dr. von Rosenstein said:
i don't understand what you mean. which control file?
Click to expand...

Simulations are controlled by control files, their file names ending (e.g.) by .sp (for SPICE) or .spc (for SPECTRE). These files may contain control constructs for the simulator, and/or netlists.

Dr. von Rosenstein said:
impedanz:RFDC_dio_T:1 {extraction, in, not, used)
Click to expand...

impedanz - being a German word - surely cannot have been automatically generated by an English simulator software, so I thought you had introduced some comment, but had forgotten to put a comment sign in front of it.
 

thanks to you i found the reason. in one of the layout.oa files in an analog_extracted folder i found:
. . . C4 PRIMLIB.cdmm.auLvs cdmm p Cpar_cap not used in extraction M 1 1903#3ahf1 sub C0 . . .

if i delete
"Cpar_cap not used in extraction"
the simulation runs without errors. but i am not sure if this has some other consequences.
do you have a suggestion how i can correct this passage?
 

Dr. von Rosenstein said:
... if i delete "Cpar_cap not used in extraction"
the simulation runs without errors. but i am not sure if this has some other consequences.
do you have a suggestion how i can correct this passage?
Click to expand...

You don't need to, I think: it's just a note to tell you that one of two parallel caps has been dismissed. Via their model files, the simulator generates its own (voltage dependent) capacitors in parallel to the individual transistors. The extractor extracts its own geometry-dependent capacitors in parallel to these transistors. Now this extractor is smart enough to find out these capacitors actually are the same ones. In order not to double-count them, it neglects one of them ... and tells you this fact.

Of course this note should have been inserted as a comment.
 

so you think the deletion of this passage has no other consequences? except that one, that the simulation runs without the error?
 

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