[SOLVED] Virtuoso ADEXL how to add mismatch to Monte Carlo design variables?

[Chenxin Jiang]

Hi there! Currently I'm trying to run Monte Carlo sampling to test my circuit design. I'm trying to add mismatch to the resistors in my circuit. The resistors I used is from the analoglib. I write a res_model.h head file an include it in the model library in the setup panel in adel. I refer to the following links:
https://community.cadence.com/caden...-ic-design/38316/monte-carlo-design-variables
https://community.cadence.com/caden...f-variable-not-defined-monte-carlo-simulation
The content of the head file is
statistics {
process {
vary RH dist=gauss std=20k percent=no
vary RL dist=gauss std=5k percent=no
}

}
And the netlist file is

Then I run Monte Carlo sampling in ADEXL, but I receive the following ERRORs
Spectre simulator stopped due to following reasons:
Error found by spectre during circuit read-in.
Error found by spectre during circuit read-in.
ERROR (SFE-1703): "/home/jiangchenxin/Desktop/RRAM_work/res_model.h" 2: Wrong number of nodes . Port instance has 2 or 3 terminals

Resolve these errors and rerun simulation.

Which part did I make mistake? How should I add user defined mismatch to the parameters in the design? Thanks!!

 

[Chenxin Jiang]

It turns out I need to place the resistor from analoglib into a subckt, then use it in my design. Refer to the following link.

Addition of source with know statistical data - Custom IC Design - Cadence Technology Forums - Cadence Community

Hi All, I would like to run a monte carlo simulation on my analog design. I know the statistical distribution (gaussian shaped) of the input signal I have to provide

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