virtual clock definition

[ee1]

Hi all,
i have read about defining virtual clocks, and correct me if i got it wrong but its main purpuse is for pure logic path (with nop clock ) from input port to output port.
my question is (if i got it right) is when i define the clock - what period time should i define?
and one more - should i define inpute and output delay for input/output ports in respect of this clock? or should i define the paths as false path in respect of this clock?
thanks.

 

[ckshivaram]

For paths going through a primary input port, the tool needs to know the frequency of the clock driving the signal in order to create a proper timing path. Similarly for output ports, the tool needs to know the frequency of the flop capturing the signal.

This is why we define a virtual clock. To give a clock relationship to paths going through IO ports.

input / output delay values ( if no clock is existing )

virtual clock can be created same as Create_clock, except that the port/pin name must not be specified !

in case if you have a purely combinational path and if you want to specify a set_input_delay or a set_output_delay for that path, then the virtual clock is used

 

[ee1]

so if i understand :
if i have IO ports i have to create a virtual clocks?
and in addition it is used for purely combinational path input/output delay?

it has 2 goals?
and what about the frequency of the virtual clock?..

thanks for the quick answer

 

[lostinxlation]

my question is (if i got it right) is when i define the clock - what period time should i define?

Check the external devices you use.

and one more - should i define inpute and output delay for input/output ports in respect of this clock?

yes

 

[avimit]

If you are defining virtual clock to constrain the combinational path of the design, it does not matter what frequency you assign to virtual clock. But it does matter that how much time do you allow for the combinational logic may be as a percentage of this clock period. And then it would matter.
Now if this block which you are constraining for pure combi logic does have other sequential logic as well, then do not forget to define false path between the clock which feeds the seq logic, i.e. the real clock and virtual clock.
Then again if a pin goes into this block and feeds both, pure combi and seq paths, then dont forget to do 'add' on 'set_input_delay' constraints you define for this pin using two clocks.
Kr,
Avi

---------- Post added at 09:29 ---------- Previous post was at 09:19 ----------

in case if you have a purely combinational path and if you want to specify a set_input_delay or a set_output_delay for that path, then the virtual clock is used

Correction: "virtual clock is used" must be corrected to --> "virtual clock may be used"
Kr,
Avi
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