hamed_sotoudi
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Hi guys,
I have designed a PCB with Xilinx Virtex6 LX75 and connected some high speed DACs to this FPGA. In this board unfortunately I used bank 16 to connect one of DACs and I got a problem regarding to clocking issue while coding. A clock comes from DAC to MMCC pin and an output from FPGA to DAC. And there is a feedback on the board to drive the MMCM feedback with external scheme. But when we started to code we found that internal banks can drive MMCM and bank16 is outside so there was an error while translating. But we designed board only according to IO planning documents and there was nothing regarding this restriction. So what we can do to solve the problem and be able to drive MMCM with bank 16 MMCC pin? is there any solution except CLOCK_DEDICATED_ROUTE = False or not?
I have designed a PCB with Xilinx Virtex6 LX75 and connected some high speed DACs to this FPGA. In this board unfortunately I used bank 16 to connect one of DACs and I got a problem regarding to clocking issue while coding. A clock comes from DAC to MMCC pin and an output from FPGA to DAC. And there is a feedback on the board to drive the MMCM feedback with external scheme. But when we started to code we found that internal banks can drive MMCM and bank16 is outside so there was an error while translating. But we designed board only according to IO planning documents and there was nothing regarding this restriction. So what we can do to solve the problem and be able to drive MMCM with bank 16 MMCC pin? is there any solution except CLOCK_DEDICATED_ROUTE = False or not?