Hello all,
I am presently working with a virtix 5 FPGA and trying to get the rocket IOs to work with reading in the data generated from my ADC. The ADC is clocked at 500MHz and I have 5 LVDS outputs, my clock at 500MHz and my data 4 bits transitioning at 250Mhz. I am then configuring the FPGA to store the data after it has been serial to parallel converted within the FPGA then I read it out later after it has taken the data so I can process my FFT in matlab. My problem is I know my ADC is working since I first took the data over a scope, but I want to speed up the measuring process by using a cool and fancy FPGA. My question is, can any help me in setting up the rocket IOs so ensure it does not miss any bits or transitions? If 1 in just 1000 samples it wrong my FFT is completely crap and I cant use it!
My present setup, which I have no clue if I am correct, is I use the rockets to sync to the incoming data (250MHz bits) only ( not the output clock). I then use the same clock recovered for the data to then clock the data into memory. My question is, is there a better way to do this? Cant i use my 500MHz clock to just clock the other data rocket IOs or since the rocket IOs work off of a PLL, I cant do that.....
Any help would be great.
Jgk