To refer to the problem mentioned in the original post, I agree that via opening should be separated from the pad copper by solder resist for regular vias. The most simple solution is a modified via padstack, with a smaller solder resist opening, e.g. 0.8 mm in the said case.
The "acid trap" problem mentioned by Mattylad remains. Another problem is that PCB manufacturer design rule checks are often performed in a simplified manner, without generating (or importing) full net list information. They can't determine same net property for copper features that aren't connected on the checked layer. In both regards, connecting via copper and pad with a track of sufficient width would help.