brayn64
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Hi,
I'm new in Cadence and I'm designing circuits with TSMC0.13um PDK. My circuit contains 8 layers, but I don't know; how to place a via between two layers? for example metal via between met1 and met2.
I'm trying to do this in schematic, may be this is not possible in the schematic? because in the vias folder of my KitDesign TSMC0.13um there are only symbolic and layout folders? if this is correct in which step, we can add vias between layers and via_gnd to take their influence in the performance of the designed circuits (during simulation with cadence).
I will appreciate your help:smile:.
I'm new in Cadence and I'm designing circuits with TSMC0.13um PDK. My circuit contains 8 layers, but I don't know; how to place a via between two layers? for example metal via between met1 and met2.
I'm trying to do this in schematic, may be this is not possible in the schematic? because in the vias folder of my KitDesign TSMC0.13um there are only symbolic and layout folders? if this is correct in which step, we can add vias between layers and via_gnd to take their influence in the performance of the designed circuits (during simulation with cadence).
I will appreciate your help:smile:.