Via & Stripline Real Impedance

[infinite_gbps]

stripline via impedance

I don't know if this is the right place to ask this but here I go.

I would like to calculate the impedance of a solid (filled) via and compare it with that of a plated via.

I know the dimensions of teh via but I just don't know the equation for resistance. It is the same for that of a strip of copper on a PCD trace just the only thing different is the way you calculate area?

Stripline R: pL/A
where: p = resistivity; L = length; A = cross sectional area

 

[FvM]

impedance of filled via

Are you discussing RF or LF (DC) properties?. For RF behaviour, the fill can be ignored. For DC and LF, you can calculate the resistance as for any conductor, if you know the material resistivity.

 

[infinite_gbps]

via stripline

Are you discussing RF or LF (DC) properties?. For RF behaviour, the fill can be ignored. For DC and LF, you can calculate the resistance as for any conductor, if you know the material resistivity.

For DC or Low Freq. characteristics I can use the equation above, correct?

I should know this but, why is the fill ignored for RF behavior?

Thanks.

EDIT: I'm actually not going to compared filled vs. plated .... just different plated geometries. How does that affect the RF behavior? Are vias just considered some sort of discontinuity (termination) as you travel down a transmission line?

 

[FvM]

The current is only flowing at the via outside due to the skin effect https://en.wikipedia.org/wiki/Skin_effect

Vias are of course acting as a discontinuity for a transmission line. Depending on the PCB stackup and design rules, they act either capacitive or inductive.

The via dimensions can be tuned to minimum reflection factor, at least in a limited frequency range. For GHz digital signals or microwave applications, they should be avoided as far as possible.

 

[infinite_gbps]

For low frequencys and DC you have the current closer to the center, correct? So just using the entire cross-sectional area is fine in my calculations, yes or no?

So if the stack-up has a through via it would be inductive and a stacked via would be capacitive, correct?

 

[FvM]

The wikipedia link tells about typical skin depths.

For an exact prediction of via reflection factors, an 3D EM simulation would be best, or a TDR measurement at the assembled board.

 

[infinite_gbps]

The wikipedia link tells about typical skin depths.

For an exact prediction of via reflection factors, an 3D EM simulation would be best, or a TDR measurement at the assembled board.

Hey, thanks you have been a great help again. I'm straying away from what I really want.

All I really need to know is if I was calculating Resistance correctly or not. If you can just give me a yes or no to this question I would appreciate it. If it is no, please correct me with how I should be calculating it.

I can use the Resistance = pL/A equation to calculate the resistance of a via? If it is a filled via (with metal) then I can use the entire cross sectional surface as the area but if it is plated then I must use that available cross sectional area. Correct?

Added after 1 minutes:

Sorry but last question, if I have a plated via that is covered by a metal Cu pad then that resistance is essentially in series and I can calculate that separately right?

 

[FvM]

The term stripline caused me to ask about RF or LF´. Stripline is usually a´RF topic.

Of course all two-dimensional calculations are simplifications. Keeping this fcat in mind, your cross section calculation should be correct.

I'm not aware of a technique to fill a via completely with conductive metal, however. Via plugging typically uses non-conductive (or possibly thermal conductive) fills.

Regarding the second question, it depends on which are the end contacts in your resistance calculation.