via spacing + optical proximity correction

Hello all,

Do any body idea about why the spacing in vias increases as the no of vias is increased...... The error we got during DFm in form of optical proximity correction recommendation..


Deepak.

Not clear. Can you please elaborate?

even i have the same doubt....
one more thing is "some technologies prefer rectangular vias than square vias, where as using 2 square vis is preferred so far I know"
can any one explain?

Regards,
Sree

Maybe it is more to do with the process limitation of fabricating vias in case of large area.

kapilsn said:

Maybe it is more to do with the process limitation of fabricating vias in case of large area.

Click to expand...

Right: The smaller the process size, the more depend min. size & spacing rules on pattern density - due to proximity effects (also) between same-layer-structures.

I wiill appreciate if anybody can upload the document suppoting exact physics behind this....

Deepak.

deepak242003 said:

I wiill appreciate if anybody can upload the document suppoting exact physics behind this....
Deepak.

Click to expand...

Hi Deepak,

just g00gle for OPC, you'll find a lot, mainly IEEE papers. Here are 2 clippings from freely accessible sources:

"Several problems arise from the small size of these features and the finite size and inherent limitations of the imaging system. First, the high frequency components required to reproduce the sharp edges in polygon features may fall outside the lens. Secondly, stray light entering the opening from one shape may find its way into another shape in close proximity, leading to a complex interaction of the electric fields of adjacent polygons. Thus the final shapes will have rounded corners and may bulge towards adjacent shapes, possibly shorting together and rendering the chip defective if the situation is bad enough." From **broken link removed**

Here's a photo how adjacent structures (here: metal) could join together:

It's published

I don't think a chip could get defective if vias (of the same connection, i.e. parallel via arrays) would join together. Foundries just don't like huge vias. Why? Probably because of CMP pb. reason.

HTH! erikl

this seems really helpful... I ll get into the detail.. and share here..

Deepak.