Via keepouts under MLCCs and inductors?

[mtwieg]

I usually have my layouts done by a third party, and they generally insist that no vias ever be placed underneath large capacitors and inductors (not referring to via in pad). See below: the pink shaded areas are via keepouts.

I can understand this caution in a couple situations, like if it's an inductor with a conductive body (very rarely the case) or if the vias reduce creepage/clearance near high voltage nodes. And this would only apply to cases where the vias are exposed through the soldermask. But the layout people are pretty adamant on enforcing these rules, regardless of whether the vias are tented or what the component is or how its used. Are there any manufacturing pitfalls I'm not aware of, or is this just pure superstition?

 

[FvM]

I opt for superstition. This sound incomprehensible. In case of HV circuits, traces and vias under a capacitor are already blocked by clearance rules, without dedicated keepouts.

The shown PCB screenshot seems to refer to low voltage circuit (30V).

 

[malli_1729]

For Inductors, i see some people use this recommendation not to put via's under Inductors, one side of inductors will have sharp changes in voltages (from SW side). But capacitors i don't see much this kind of considerations.

 

[mtwieg]

The keepouts are defined in the component footprint, so any 2220 size capacitor will have the keepout by default, regardless of whether it's rated for 5V or 500V, and regardless of what the actual applied voltage is.

I just wanted to check if there was some guideline in IPC-2221 that covers this that I was unaware of. If not, I'm just going to overrule them next time.

 

[NIKHILRAJ]

for switching inductors-non shielded , better to avoid other net vias under them or in the close proximity- may help to avoid coupling - , For big package capacitors - say from 1206- it should be ok to place vias