VHLD Serial Communication Pointers

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


ENTITY light_tester is
	GENERIC(
		pwm_pulses  : integer := 10;  --4096--number of spi slaves
		transmit_pulses : integer := 5); --192--data bus width
	PORT(
		clock :	in			std_logic;										--SYS Clock
		gsclk	:	buffer	std_logic := '0';								--GS Clock
		dcprg	:	out		std_logic := '0';								--DC Program (keep low) for future development
		sclk	:	buffer	std_logic := '0';								--Shift load clock
		blank	:	out		std_logic := '0';								--Blank outputs/zero PWM counter
		vprg	:	out		std_logic := '0';								--EEPROM Program (keep low) for future development
		xlat	:	buffer	std_logic := '0';								--latch new data use when blank is high
		data	:	out		std_logic := '0');							--data sent out
end light_tester;

ARCHITECTURE logic OF light_tester IS
	
begin
	process (clock)						--clocks pwm of TLC5940 using 1/2 FPGA clock freq (25 MHz => 12.5 MHz)
		variable gs_counter : integer range 0 to pwm_pulses*2+3 := 0;
		variable senddata : boolean := true;
		variable data_to_send : std_logic_vector(0 to 7) := ('1', '1', '0', '1', '0', '0', '1', '0');
	begin
	
		if(clock'EVENT and clock = '1') then
			case gs_counter IS
				when pwm_pulses*2 =>		-- done with clocking in data
					gs_counter := gs_counter+1;
					blank <= '1';				--set blank high to reset the TLC5940 PWM counter
				when pwm_pulses*2+1 =>
					xlat <= '1';				--set xlat high to latch new data
					gs_counter := gs_counter+1;
				when pwm_pulses*2+2 =>		--toggle xlat and blank and reset to start over
					xlat <= '0';
					blank<= '0';
					gs_counter :=0;
					senddata :=true;        -- send new data next round

				when transmit_pulses*2 =>	--last transmitted serial data so dont transmit any more
					senddata :=false;
					gs_counter := gs_counter+1;
					gsclk <= not gsclk;		--toggle pwm clock
						
				when others => 				--clock 4096 pwm pulses
					gs_counter := gs_counter+1;
					gsclk <= not gsclk;		--toggle pwm clock
					if (senddata) then		--only send data when you haven't transmitted all the bits
						sclk <= not sclk;		--toggle serial data clock
					end if;
			end case;
		end if;
		
		if (clock'event and clock = '0' and senddata) then --clock is 0 => load new data
			data<=data_to_send(gs_counter);				--load data to be transmitted
																	--right now this is just dummy data
		end if;
	end process; 
	
end logic;

process(clk)
begin
  if rising_edge(clk) then
    if sendata then
      data<=data_to_send(gs_counter)
    end if;
  end if;
end process;