VHDL - What am I doing wrong?

[jelydonut]

vhdl to_integer

Im trying to make a 32x8 memory, but can only write, cannot read. I need the data bus to be bidirectional as well..

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;

entity memories is
port(
address : in std_logic_vector(4 downto 0);
read : in std_logic;
write : in std_logic;
data : inout std_logic_vector(7 downto 0);
);
end memories;

architecture memories of memories is
type Memory_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Addr : Memory_Image(0 to 31);
begin
process (read, write)
begin
if (read = '1') then
data <= Addr(to_integer(unsigned(address)));
end if;
if (write = '1') then
Addr(to_integer(unsigned(address))) <= data;
end if;
end process;
end memories;

 

[irum4]

to_integer vhdl

You must specify data output value

if (read = '1') then
data <= Addr(to_integer(unsigned(address)));
else-- :!:
data <= (others =>'Z');--:!:
end if;

 

[vomit]

to_integer vhdl library

Im trying to make a 32x8 memory, but can only write, cannot read. I need the data bus to be bidirectional as well..
architecture memories of memories is
type Memory_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Addr : Memory_Image(0 to 31);
begin
process (read, write)
begin
if (read = '1') then
data <= Addr(to_integer(unsigned(address)));
end if;
if (write = '1') then
Addr(to_integer(unsigned(address))) <= data;
end if;
end process;
end memories;

Also you need to add address to the sensitivity list of the process so you read the new address when it changes while read stays '1'.

There's also no x handling. If to_x01(write)='X' the current address could be invalidated so you should dump "XXX..XX" into that memory location.
If the address is invalid while writing the entire memory should be invalidated.

Finally if you only use 1 process for accessing (r/w) the memory, you can put the memory contents into a variable instead of a signal, that's much more efficient for your simulator (PC memory usage).

If you just want a good SRAM model (like it seems to me) check out
**broken link removed**

 

[Al Farouk]

vhdl using to_integer

Try the following
1- Avoid the inout portdescription and useseparat ports for them. Finally if you want them to share the same data bus use Tri stat buffer enabled by Read and Write separatley.

2-
architecture memories of memories is
type Memory_Image is array (31 downto 0) of std_logic_vector(7 downto 0);
signal Addr : Memory_Image;
begin
process (read, write)
begin
if (read = '1') then
data <= Memory_Image(to_integer(address));
end if;
if (write = '1') then
Memory_Image(to_integer(address)) <= data;
end if;
end process;
end memories;