vhdl unconstrained array port

I want to create a new VHDL type inside a package called "2d_array" .
This type will be used as an array entity intput port (or output port).
I want the port's diementions to be unconstrained in order be able to define the exact size during compilation with 2 entity generic :
"2d_array_port_depth" and "2d_array_port_width".

Is it possible with VHDL?
If yes, please show me an example.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE 2d_array_pkg IS

TYPE 2d_array IS ARRAY(15 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);

END 2d_array_pkg;

with VHDL 1993, you cannot leave all dimensions unconstrained, only the outer most one. eg:

type 2d_array_t is array(integer rage <>) of std_logic_vector(31 downto 0);

but with VHDL 2008, you can do this:

type 2d_array_t is array(integer rage <>) of std_logic_vector;

signal my_input : 2d_array_t(15 downto 0, 31 downto );

but you will need a compiler with 2008 support. otherwise you'll have to put the generics as constants in a package to define the type.

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with VHDL 1993, you cannot leave all dimensions unconstrained, only the outer most one. eg:

type 2d_array_t is array(integer rage <>) of std_logic_vector(31 downto 0);

but with VHDL 2008, you can do this:

type 2d_array_t is array(integer rage <>) of std_logic_vector;

signal my_input : 2d_array_t(15 downto 0, 31 downto );

but you will need a compiler with 2008 support. otherwise you'll have to put the generics as constants in a package to define the type.

Thanks for replying dftrtl,
However - this doesn't help.

You define an array of known and constant diementions!
I want to define a type that can be used as an array input port with the exact diementions set only during compile time using entity generics...

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TrickyDicky,

So with VHDL 93 we cannot create an array input port with completely generic diementions?

you can create a true 2d array with vhdl 93

type my_2d_array_t is array(integer range <>, integer range <>) of integer;

and declare:

signal a : my_2d_array_t(0 to N, 0 to M);

but I wouldnt recommend using std_logic, as it is a pain to map to std_logic_vectors, as you have to assign it bit by bit if you want a whole array.

I don't understand what you mean...
this is a generic array definitions:
But that's inside an entity in the signal definitions area!
I want to be able to define an entity port in the same manor...

unless its VHDL 2008, you cant. You have to make the generics constants inside a package and declare the type in the package too.

In VHDL 2008, the actual width of an unconstrained component port can be set by connecting a constrained signal in the instantiation, you won't even need generics for it. I didn't check it, but it's discussed as an example in a text book VHDL 2008 - Just the New Stuff.

Please show me an example (using VHDL 2008) of what I want to do (explained in post #6)...

type GENERIC_ARRAY is array (natural range <> ) of unsigned;
signal SOME_GENERIC_ARRAY : GENERIC_ARRAY(0 to GENERIC_DEPTH - 1 , GENRIC_WIDTH - 1 downto 0) ;