shaiko
Advanced Member level 5
Hello,
In my design I use arrays of unsigned vectors. For this purpose, I define an unconstrained array type inside a package as follows:
In the source file where I use this type I define the signal as follows:
The code compiles successfully with Modelsim / Questa , Vivado and Quartus.
However, when I try to compile it with VCS - It fails on the line where the signal is declared with an obscure message:
"Syntax error detected during VHDL parsing".
* I verified that the tool is set to VHDL 2008.
What might cause such an error ?
In my design I use arrays of unsigned vectors. For this purpose, I define an unconstrained array type inside a package as follows:
Code:
type generic_array_unsigned_1d is array ( natural range <> ) of unsigned ;
Code:
signal some_array_of_unsigned : generic_array_unsigned_1d is array ( 0 to some_depth - 1 ) ( some_width - 1 downto 0 ) ;However, when I try to compile it with VCS - It fails on the line where the signal is declared with an obscure message:
"Syntax error detected during VHDL parsing".
* I verified that the tool is set to VHDL 2008.
What might cause such an error ?