VHDL unconstrained array in VCS

[shaiko]

Hello,

In my design I use arrays of unsigned vectors. For this purpose, I define an unconstrained array type inside a package as follows:

type generic_array_unsigned_1d is array ( natural range <> ) of unsigned ;

In the source file where I use this type I define the signal as follows:

signal some_array_of_unsigned : generic_array_unsigned_1d is array ( 0 to some_depth - 1 ) ( some_width - 1 downto 0 ) ;

The code compiles successfully with Modelsim / Questa , Vivado and Quartus.

However, when I try to compile it with VCS - It fails on the line where the signal is declared with an obscure message:
"Syntax error detected during VHDL parsing".
* I verified that the tool is set to VHDL 2008.

What might cause such an error ?

 

[TrickyDicky]

Id say the tool doesnt support unconstrained arrays. But I dont use VCS, and cannot find documentation about 2008 support.
Have you raised a support ticket?

 

[shaiko]

Yes. Waiting to hear back...